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1. 发明公开

EP2596422A1 A CIRCULAR FLOATING-POINT NUMBER GENERATOR AND A CIRCULAR FLOATING-POINT NUMBER ADDER 审中-公开
标题翻译：一个循环浮点数生成器和一个循环浮点数加法器
公开(公告)号：EP2596422A1
公开(公告)日：2013-05-29
申请号：EP10854116.0
申请日：2010-07-01
申请人： Telefonaktiebolaget LM Ericsson (publ)
发明人： ASANAKA, Kazunori
IPC分类号： G06F7/483
CPC分类号： G06F7/4833 , G06F7/485 , G06F7/49915 , H03M7/24
摘要： One aspect of the present invention will provide a circular floating-point number generator (400) for generating, from an input fixed-point number, a circular floating-point number including sign-bit field (S), exponent field (E), and circular-mantissa field (M). The generator assigns the input bits in the fixed-point number to a plurality of slots, generates the sign-bit field (S), generate the exponent field (E) based on a bit position of a leading significant bit, and generate the mantissa field (M) by extracting a first bit group and a second bit group and by providing a start bit of the first bit group after a last bit of the second bit group.
摘要翻译：本发明的一个方面将提供一种循环浮点数生成器（400），用于从输入的定点数生成包括符号位字段（S），指数字段（E），循环字段和圆形尾数字段（M）。生成器将定点数中的输入比特分配给多个时隙，生成符号比特字段（S），基于前导有效比特的比特位置生成指数字段（E），并生成尾数通过提取第一比特组和第二比特组，并且通过在第二比特组的最后比特之后提供第一比特组的开始比特来提供字段（M）。

2. 发明公开

EP2140348A2 PROCESSOR, METHOD AND COMPUTER PROGRAM 审中-公开
标题翻译：处理器，方法和计算机程序
公开(公告)号：EP2140348A2
公开(公告)日：2010-01-06
申请号：EP08718099.8
申请日：2008-03-20
申请人： Telefonaktiebolaget LM Ericsson (publ)
发明人： ASANAKA, Kazunori
IPC分类号： G06F9/38
CPC分类号： G06F9/383 , G06F9/3836 , G06F9/3857
摘要： To accelerate processing speed of a processor while keeping increased complexity in the processor's circuitry to a minimum. A processor is offered, comprising a decoder which sequentially acquires and decodes an instruction from a program, including an instruction of a first type and a second type, which are classified according to a property of data upon which the instruction is to operate; a first operation unit which sequentially receives from the decoder, and executes, the instruction of the first type; an operand processing circuit which substitutes a variable value, which is set into a register that is associated with the first operation unit, and which is included within an operand of the instruction of the second type, with a constant; a buffer which queues the instruction of the second type that has been decoded by the decoder, and the operand thereof has been substituted by the operand processing circuit; and a second operation unit which sequentially receives from the buffer, and executes, the instruction of the second type. Methods and computer program for implementing the methods are also disclosed.

3. 发明公开

EP3202045A1 METHOD AND DEVICE FOR CALCULATING A CRC CODE IN PARALLEL 审中-公开
标题翻译：用于并行计算CRC码的方法和设备
公开(公告)号：EP3202045A1
公开(公告)日：2017-08-09
申请号：EP14780518.8
申请日：2014-10-03
申请人： Telefonaktiebolaget LM Ericsson (publ)
发明人： ASANAKA, Kazunori , AALTO, Christer
IPC分类号： H03M13/09
CPC分类号： H03M13/091 , H03M13/617
摘要： The disclosure relates to a method performed in a cyclic redundancy check, CRC, device for calculating, based on a generator polynomial G(x), a CRC code for a message block. The method comprises receiving n segments of the message block in forward order or in reverse order, wherein at least one segment is received in reverse order; calculating for each of the n segments a respective segment CRC code based on the generator polynomial G(x), wherein each segment CRC is calculated according to the received order of the segment; aligning each of the n segment CRC codes; and calculating the CRC code for the message block by adding together each of the aligned n segment CRC codes. The disclosure also relates to a device, computer program and computer program product.
摘要翻译：本公开涉及一种在循环冗余校验CRC装置（300）中执行的用于基于生成多项式G（x）计算消息块的CRC码的方法（200）。所述方法（200）包括以正向顺序或以相反顺序接收（201）所述消息块的n个段，其中以相反顺序接收至少一个段; 基于所述生成多项式G（x）为所述n个分段中的每一个计算（202）相应的分段CRC码，其中根据所述分段的接收顺序来计算每个分段CRC; 对准（203）n个分段CRC码中的每一个; 以及通过将所述对齐的n个分段CRC码中的每一个加在一起来计算（204）所述消息块的CRC码。本公开还涉及设备（300），计算机程序和计算机程序产品。

4. 发明公开

EP2553569A1 DATA SHIFTER AND CONTROL METHOD THEREOF, MULTIPLEXER, DATA SIFTER, AND DATA SORTER 审中-公开
标题翻译：数据转换器及其控制方法，多路复用器，数据筛选器和数据分拣器
公开(公告)号：EP2553569A1
公开(公告)日：2013-02-06
申请号：EP10848971.7
申请日：2010-03-31
申请人： Telefonaktiebolaget LM Ericsson (publ)
发明人： ASANAKA, Kazunori
IPC分类号： G06F7/76
CPC分类号： G06F7/76 , G06F5/015 , G06F7/24 , G06F7/762
摘要： A data shifter (10) includes plural stages each including N elemental units (20), each preliminarily assigned a one-bit value c and a positive integer q. The mth elemental unit in the pth stage inputs target data and destination data representing a lane number where Data(p,m), a logical OR of the input target data, should be routed to; compares the qth bit from the LSB of Des(p,m), a logical OR of the input destination data, with the c; and outputs, based on the comparison result, both Data(p,m) or the value 0 and Des(p,m) or the value 0 bound for the mth elemental unit in the next stage, and if m-1+2
q-1 q-1 )th elemental unit in the next stage. The shifter inputs both the N-lane data sequences to be processed as the target data and the destination data of each data sequence into the N elemental units in the first stage, and outputs, as shifted output data of the mth lane, a logical OR of the target data which the elemental units in the last stage output bound for the mth elemental unit in the next stage.
摘要翻译：数据移位器（10）包括多个级，每个级包括N个基本单元（20），每个基本单元预先分配一位值c和正整数q。第p级中的第m个基本单元输入表示通道编号的目标数据和目的地数据，其中输入目标数据的逻辑或的Data（p，m）应该被路由到; 将来自Des（p，m）的LSB的第q位（输入目的地数据的逻辑OR）与c进行比较; 并根据比较结果输出下一级的第m个元素单元的Data（p，m）或值0和Des（p，m）或值0，并且如果m-1 + 2 q -1

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