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1. 发明公开

EP0984356A1 A carry lookahead adder having a reduced fanout architecture 审中-公开
标题翻译：具有减少扇出体系结构的进位前瞻加法器
公开(公告)号：EP0984356A1
公开(公告)日：2000-03-08
申请号：EP99108779.2
申请日：1999-05-03
申请人： Hewlett-Packard Company
发明人： Dix, Gregory S. , Martin, Robert J. , Lin, Linda L.
IPC分类号： G06F7/50
CPC分类号： G06F7/508 , G06F2207/5063
摘要： A carry lookahead adder (100) having a reduced internal block fanout which is achieved efficiently in terms of the silicon area needed to implement the carry lookahead adder (100). The carry lookahead adder (100) of the present invention is characterized by a modified binary tree structure having carry generate/propagate signal operators (21, 31, 35, 41, 44, 48, 51, 23, 25, 33, 37, 42, 46, 75, 76, 77, 78, 79, 80, 81, 82, 51-54, 83-86, 55, 57, 59, 63, 56, 58, 61, 64) located in such a manner that the maximum internal block fanout is equal to (adder width)/8 for adders having a width of at least 16 bits. For adders having a width of less than 16 bits, the internal block fanout is 2. The routing complexity is increased in order to implement redundant overlapping carry generate/propagate operations which, in turn, decreases the internal block fanout of the adder. However, increases in routing complexity can be accomplished within the minimum X-by-Y area of each stage of the adder. Therefore, the overall performance of the carry lookahead adder (100) of the present invention can be optimized while meeting minimum area requirements.
摘要翻译：具有减少的内部扇区扇出的进位前瞻加法器（100），其在实现进位先行加法器（100）所需的硅面积方面被有效地实现。本发明的进位前瞻加法器（100）的特征在于具有进位产生/传播信号运算器（21,31,35,41,44,48,51,23,25,33,37,42）的改进的二进制树结构，46,75,76,77,78,79,80,81,82,51-54,83-86,55,57,59,63,56,58,61,64），其位置如下对于宽度至少为16位的加法器，最大内部扇出扇出等于（加法器宽度）/ 8。对于宽度小于16位的加法器，内部模块扇出为2.增加布线复杂度以实现冗余重叠进位产生/传播操作，这进而减少了加法器的内部扇出扇出。但是，路由复杂度的增加可以在加法器的每个级的最小X-Y区域内完成。因此，本发明的进位前瞻加法器（100）的总体性能可以在满足最小面积要求的同时被优化。

2. 发明授权

EP3246814B1 LOGIC CIRCUIT 失效转让
公开(公告)号：EP3246814B1
公开(公告)日：2018-11-28
申请号：EP16169818.8
申请日：2016-05-16
申请人： Hitachi, Ltd. , Yissum Research Development Company of the Hebrew University of Jerusalem Ltd. , Université de Liège
发明人： Gonzalez-Zalba, Miguel Fernando , Kaxiras, Stefanos , Själander, Magnus , Remacle, Françoise , Klymenko, Mykhailo , Levine, Raphael D.
IPC分类号： G06F7/506
CPC分类号： G06F7/506 , G06F2207/3812 , G06F2207/5063
摘要： A logic circuit including a plurality of logic blocks is disclosed. Each logic block is operable in a first number base (for example binary) having a first number of logic levels and a second, different number base (for example quaternary) having a second, different number of logic levels. Each logic block is arranged to receive at least one digit in a respective number base. The logic circuit also includes a controller arranged to cause each logic block to output a result in its respective number base. Each logic block may include at least one electronic device capable of exhibiting N logic levels, where N is a positive real integer greater than two.

3. 发明公开

EP3246814A1 LOGIC CIRCUIT 失效转让
标题翻译：逻辑电路
公开(公告)号：EP3246814A1
公开(公告)日：2017-11-22
申请号：EP16169818.8
申请日：2016-05-16
申请人： Hitachi, Ltd.
发明人： Gonzalez-Zalba, Miguel Fernando , Kaxiras, Stefanos , Själander, Magnus
IPC分类号： G06F7/506
CPC分类号： G06F7/506 , G06F2207/3812 , G06F2207/5063
摘要： A logic circuit including a plurality of logic blocks is disclosed. Each logic block is operable in a first number base (for example binary) having a first number of logic levels and a second, different number base (for example quaternary) having a second, different number of logic levels. Each logic block is arranged to receive at least one digit in a respective number base. The logic circuit also includes a controller arranged to cause each logic block to output a result in its respective number base. Each logic block may include at least one electronic device capable of exhibiting N logic levels, where N is a positive real integer greater than two.
摘要翻译：公开了包括多个逻辑块的逻辑电路。每个逻辑块可在具有第一数量的逻辑电平的第一数字基数（例如二进制）和具有第二不同数量的逻辑电平的第二不同数量基数（例如四元数）中操作。每个逻辑块被安排成在相应的数字库中接收至少一个数字。该逻辑电路还包括控制器，该控制器被设置为使每个逻辑块在其各自的数字库中输出结果。每个逻辑块可以包括至少一个能够呈现N个逻辑电平的电子设备，其中N是大于2的正实数。

4. 发明公开

EP1296223A2 Adder incrementer circuit 审中-公开
标题翻译： Addier- und Inkrementierschaltung
公开(公告)号：EP1296223A2
公开(公告)日：2003-03-26
申请号：EP02256594.9
申请日：2002-09-23
申请人： Broadcom Corporation
发明人： Evans, Richard James
IPC分类号： G06F7/50
CPC分类号： G06F7/508 , G06F7/5055 , G06F7/506 , G06F2207/5063
摘要： In association with a circuit for adding binary numbers, it is often useful to increment the sum by a value of 1, for example on a conditional basis. Each of the combined adder and incrementer circuits embodying the invention also provides an output indicating whether a CarryOut signal resulted from the incrementing operation, or whether the Carryout signal resulted from the addition. The preferred embodiments utilize prefix-type adder circuits using a single carry chain. Alternate embodiments generate a CarryOut signal as a function of the incrementing operation, using either generate and propagate signals or from generate and kill signals from the carry chain.
摘要翻译：与用于添加二进制数的电路相关联，例如在有条件的基础上将总和增加值1通常是有用的。体现本发明的组合加法器和加法器电路中的每一个还提供一个指示输入信号是由增量操作产生的输出还是由加法产生的输出信号。优选实施例使用使用单个进位链的前缀式加法器电路。替代实施例使用生成和传播信号或从来自进位链的信号产生和消除作为递增操作的函数产生CarryOut信号。

5. 发明公开

EP0467524A2 Lookahead adder 失效
标题翻译： Übertragvorgriffsaddierer。
公开(公告)号：EP0467524A2
公开(公告)日：1992-01-22
申请号：EP91305324.5
申请日：1991-06-12
申请人： Hewlett-Packard Company
发明人： Lamb, Joel D.
IPC分类号： G06F7/50
CPC分类号： G06F7/508 , G06F2207/5063
摘要： In a lookahead adder of the type wherein carry signals for successive stages of the adder are derived by a pyramid of hierarchically-arranged logic circuits, supplemented by carry signals from intermediate ones of the adder stages. The need to rely on such intermediate carry signals is dispensed with by additional non- hierarchically-arranged logic circuits whose outputs provide the information previously derived from intermediate carry outputs.
摘要翻译：在这种类型的前瞻加法器中，其中用于加法器的连续级的进位信号由分层布置的逻辑电路的金字塔导出，并由来自加法器级的中间加法器的进位信号补充。通过附加的非分层布置的逻辑电路来省去对这种中间进位信号的依赖，其输出提供先前从中间进位输出导出的信息。

6. 发明公开

EP3289445A4 FLOATING POINT COMPUTATION APPARATUS AND METHOD 有权
公开(公告)号：EP3289445A4
公开(公告)日：2018-05-30
申请号：EP16802335
申请日：2016-02-15
申请人： HUAWEI TECH CO LTD
发明人： HO HUONG , KAFROUNI MICHEL
IPC分类号： G06F9/38 , G06F7/506
CPC分类号： G06F7/485 , G06F7/506 , G06F2207/5063
摘要： A method comprises receiving a first N-bit unsigned number and a second N-bit unsigned number, receiving a control signal indicating a m-bit shifting operation and processing the first N-bit unsigned number, the second N-bit unsigned number and the control signal in an add-and-shift apparatus, wherein an addition/subtraction operation and the m-bit shifting operation are performed in parallel in the add-and-shift apparatus.

7. 发明公开

EP2013705A1 ADDITIONNEUR N BITS ET PROCÉDÉ D'ADDITION CORRESPONDANT 有权
标题翻译： N位加法器和相关联的加入法
公开(公告)号：EP2013705A1
公开(公告)日：2009-01-14
申请号：EP07731319.5
申请日：2007-04-19
申请人： S.A.R.L. Daniel Torno
发明人： TORNO, Daniel
IPC分类号： G06F7/506 , G06F7/508
CPC分类号： G06F7/506 , G06F7/508 , G06F2207/5063
摘要： Adder for adding input signals comprising first (A) and second (B) binary input numbers, with N bits each. Said adder comprises determination means (MDET) capable of determining the bits of the sum of the input signals comprising estimating means including estimating blocks (BESTi) connected in series, each estimating block being capable of estimating each bit of said sum, and correction means (MCORi) capable of generating a correction signal so as to correct each estimated bit of said sum after each estimate, each correction signal of an estimated bit rank i of the sum being generated using the last rank i-1 estimated and corrected bit of the sum, the correction signal of said last rank i- 1 bit, and the last estimated and corrected rank i-2 bit of the sum.

8. 发明公开

EP0929862A4 LOGIC ELEMENTS FOR INTERLACED CARRY/BORROW SYSTEMS HAVING A UNIFORM LAYOUT 失效
标题翻译：逻辑元素适合随身携带交织/传输系统，统一布局
公开(公告)号：EP0929862A4
公开(公告)日：2001-08-22
申请号：EP96912409
申请日：1996-03-11
申请人： PERKEL MANLEY , GRUNDLAND NATHAN
发明人： GRUNDLAND NATHAN
IPC分类号： G06F7/50 , G06F7/508
CPC分类号： G06F7/508 , G06F2207/3876 , G06F2207/5063
摘要： Logic elements (20) for use in carry/borrow and comparator systems, which operate in accordance with the IMPLY logical relationship. Utilization of the IMPLY logical relationship overcomes the inherent complication of inversion so that it becomes an effective benefit, making possible uniform carry system layouts with uniform logic elements using a newly defined gate pair combination in general. The gate pair logic elements (20) provide a novel carry-propagate signal P which includes a redundant carry-generate signal G, thereby defining a novel carry-integrate signal I (Ao). The novel carry-integrate signal I (Ao) together with the carry-generate signal G (Bo) define a signal pair utilized in succeeding carry levels which are organized in a simplified fashion.

9. 发明授权

EP0467524B1 Lookahead adder 失效
标题翻译： Lookahead加法器
公开(公告)号：EP0467524B1
公开(公告)日：1997-04-23
申请号：EP91305324.5
申请日：1991-06-12
申请人： Hewlett-Packard Company
发明人： Lamb, Joel D.
IPC分类号： G06F7/50
CPC分类号： G06F7/508 , G06F2207/5063

10. 发明公开

EP0442665A3 Lookahead adder with universal logic gates 失效
标题翻译： LOOKAHEAD ADDER与通用逻辑门
公开(公告)号：EP0442665A3
公开(公告)日：1993-01-07
申请号：EP91301012.0
申请日：1991-02-07
申请人： Hewlett-Packard Company
发明人： Lamb, Joel D.
IPC分类号： G06F7/50 , H03K19/094
CPC分类号： G06F7/508 , G06F2207/3876 , G06F2207/5063 , H03K19/0948
摘要： A lookahead adder with identical logic gates (MCLA) in all but the first of its lookahead sections. All such identical gates implement the logic function M = X + Y.Z.

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