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1. 发明授权

EP3246814B1 LOGIC CIRCUIT 失效转让
公开(公告)号：EP3246814B1
公开(公告)日：2018-11-28
申请号：EP16169818.8
申请日：2016-05-16
申请人： Hitachi, Ltd. , Yissum Research Development Company of the Hebrew University of Jerusalem Ltd. , Université de Liège
发明人： Gonzalez-Zalba, Miguel Fernando , Kaxiras, Stefanos , Själander, Magnus , Remacle, Françoise , Klymenko, Mykhailo , Levine, Raphael D.
IPC分类号： G06F7/506
CPC分类号： G06F7/506 , G06F2207/3812 , G06F2207/5063
摘要： A logic circuit including a plurality of logic blocks is disclosed. Each logic block is operable in a first number base (for example binary) having a first number of logic levels and a second, different number base (for example quaternary) having a second, different number of logic levels. Each logic block is arranged to receive at least one digit in a respective number base. The logic circuit also includes a controller arranged to cause each logic block to output a result in its respective number base. Each logic block may include at least one electronic device capable of exhibiting N logic levels, where N is a positive real integer greater than two.

2. 发明公开

EP3246814A1 LOGIC CIRCUIT 失效转让
标题翻译：逻辑电路
公开(公告)号：EP3246814A1
公开(公告)日：2017-11-22
申请号：EP16169818.8
申请日：2016-05-16
申请人： Hitachi, Ltd.
发明人： Gonzalez-Zalba, Miguel Fernando , Kaxiras, Stefanos , Själander, Magnus
IPC分类号： G06F7/506
CPC分类号： G06F7/506 , G06F2207/3812 , G06F2207/5063
摘要： A logic circuit including a plurality of logic blocks is disclosed. Each logic block is operable in a first number base (for example binary) having a first number of logic levels and a second, different number base (for example quaternary) having a second, different number of logic levels. Each logic block is arranged to receive at least one digit in a respective number base. The logic circuit also includes a controller arranged to cause each logic block to output a result in its respective number base. Each logic block may include at least one electronic device capable of exhibiting N logic levels, where N is a positive real integer greater than two.
摘要翻译：公开了包括多个逻辑块的逻辑电路。每个逻辑块可在具有第一数量的逻辑电平的第一数字基数（例如二进制）和具有第二不同数量的逻辑电平的第二不同数量基数（例如四元数）中操作。每个逻辑块被安排成在相应的数字库中接收至少一个数字。该逻辑电路还包括控制器，该控制器被设置为使每个逻辑块在其各自的数字库中输出结果。每个逻辑块可以包括至少一个能够呈现N个逻辑电平的电子设备，其中N是大于2的正实数。

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