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    • 3. 发明授权
      EP0237571B1 MEMORY-LINKED WAVEFRONT ARRAY PROCESSOR 失效
    • MEMORY-LINKED WAVEFRONT ARRAY PROCESSOR
    • 存储器连接的WAVEFRONT ARRAY处理器
    • EP0237571B1
    • 1992-04-29
    • EP86906519.3
    • 1986-09-17
    • THE JOHNS HOPKINS UNIVERSITY
    • DOLECEK, Quentin, E.
    • G06F15/00 , G06F15/16
    • G06F15/8046 , G06F15/17381
    • A Memory-Linked Wavefront Array Processor (MWAM) which computes a broad range of signal processing, scientific and engineering problems at ultra-high speed. The memory-linked wavefront array processor is an array of identical programmable processing elements (34) linked together by dual-port memory elements (32) that contain a set of special purpose control flags (126). All communication in the network is done asynchronously via the linking memory elements (32), thus providing asynchronous global communication with the processing array. The architecture allows coefficients, intermediate calculations and data used in computations to be stored in the linking elements between processing stages (34). The novel architecture also allows coefficients, intermediate calculations and data to be passed between the processing elements (34) in any desired order not restricted by the order data is to be used by the receiving processing element (34). Further, each processing element (34) is capable of simultaneous arithmetic computation, multi-direction communication, logic discussions, and program control modifications.
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 9. 发明公开
      EP1278128A2 Systolic array device 审中-公开
    • Systolic array device
    • Systolische Matrixvorrichtung
    • EP1278128A2
    • 2003-01-22
    • EP02015672.5
    • 2002-07-17
    • NTT DoCoMo, Inc.
    • Asai, Takahiro, NTT DoCoMo, Inc. Intel.Prop.Dept. , Matsumoto, Tdadashi, NTT DoCoMo, Inc. Int.Pty.Dep. , Tomisato, Shigeru, NTT DoCoMo, Inc.Intel.Prop
    • G06F15/80
    • G06F15/8046
    • When a plurality of reference signal series are handled with the same input signal series during processing of an RLS algorithm based on QR decomposition, an object is to handle the plurality of reference signal series simultaneously. When performing processing of a sequential least-squares algorithm based on QR decomposition, to a configuration comprising a plurality of boundary cells (empty circles) which calculate appropriate rotation parameters for transformations based on Givens rotation, a plurality of internal cells (squares) which cause rotation of elements of a received data vector using the calculated values of the boundary cells (empty circles), and a final cell (double circles) which derives the a posteriori estimated error from the calculated values of the boundary cells (empty circles) and internal cells (squares), additional internal cells (squares) within 21 are connected so as to receive signals output from each of the internal cells (squares) arranged in the end cell column to which the signal series is input, and to the final cell (double circles) is connected an additional final cell (double circles) within 21, so as to receive the calculated values from the boundary cells (empty circles) and the calculated values from the additional internal cells (square) input to the additional final cell (double circles).
    • 当在基于QR分解的RLS算法的处理期间以相同的输入信号序列处理多个参考信号序列时，目标是同时处理多个参考信号序列。 在进行基于QR分解的顺序最小二乘法算法的处理时，对于包含多个边界单元（空圆）的配置，该边界单元计算用于基于Givens旋转的变换的适当的旋转参数，导致多个内部单元（正方形） 使用计算出的边界单元格（空心圆）的接收数据向量的元素的旋转，以及从边界单元（空心圆）和内部的计算值导出后验估计误差的最终单元（双圆） 连接21个内的单元（正方形），附加的内部单元（正方形），以接收从布置在输入信号系列的端单元列的每个内部单元（正方形）输出的信号和最终单元 双圆）在21内连接另外的最终单元（双圆），以便从边界单元（空圆）和 来自附加内部单元格（平方）的输入到附加最终单元格（双圆圈）的计算值。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 10. 发明公开
      EP0708407A1 Signal processor 失效
    • Signal processor
    • Signalprozessor
    • EP0708407A1
    • 1996-04-24
    • EP95116589.3
    • 1995-10-20
    • MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    • Ninomiya, Kazuki , Sumida, Keizo , Miyaki, Jiro , Nishiyama, Tamotsu
    • G06F15/80
    • G06F15/8046 , G06F15/8023
    • An improved signal processor is disclosed which is suitable for convergence processing of images that achieves parallel processing with a smaller bus structure. An arithmetic array is provided which is formed of ten arithmetic cells capable of concurrently operating. Each arithmetic cell is specified by a denotation of E[x(column number),y(row number)] where the column number x is 1 ≦ x ≦ 4 and the row number y is x ≦ y ≦ 4. Each arithmetic cell has a multiplier and an adder for multiply-add operation. An arithmetic cell, specified by E[x,y] where 2 ≦ x ≦ 4 and x ≦ y ≦ 4, receives data from an E[x-1, y] arithmetic cell via a direct bus as well as from an E[x-1, y-1] arithmetic cell via an oblique bus. For example, when pixel data items as to four pixels horizontally arranged in an image are fed to the four arithmetic cells in the first column, the arithmetic cell in the fourth column provides a 4-tap horizontal filter operation result.
    • 公开了一种改进的信号处理器，其适用于以较小的总线结构实现并行处理的图像的收敛处理。 提供由能够同时操作的十个算术单元形成的运算阵列。 每个算术单元通过EÄx（列号），y（行号）Ü的指定来指定，其中列号x为1
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
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