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    • 3. 发明公开
    • DISPLAY DEVICE
    • 显示设备
    • EP3321989A1
    • 2018-05-16
    • EP17200505.0
    • 2017-11-08
    • Samsung Display Co., Ltd.
    • CHOUNG, JiyoungKIM, ArongLEE, Yeonhwa
    • H01L51/52H01L27/32
    • H01L51/5228G09G3/3233G09G2300/0426G09G2300/0809H01L27/3246H01L27/3279H01L51/5012H01L51/5056H01L51/5072H01L51/5088H01L51/5092H01L51/5206H01L51/5225H01L51/5237H01L51/5253H01L51/56H01L2251/5392
    • A display device includes: a substrate (100); a first pixel electrode (211) disposed on the substrate; a second pixel electrode (212) disposed on the substrate; a pixel-defining layer (120) disposed on the substrate, the pixel-defining layer comprising: a portion disposed between the pixel electrodes; and openings respectively overlapping the pixel electrodes; a first intermediate layer (221) on the first pixel electrode, the first intermediate layer comprising a first emission layer; a second intermediate layer (222) on the second pixel electrode, the second intermediate layer comprising a second emission layer spaced apart from the first emission layer; a first opposite electrode (231) on the first intermediate layer; a second opposite electrode (232) on the second intermediate layer, the second opposite electrode being spaced apart from the first opposite electrode; and a wiring layer (130) overlapping the portion of the pixel-defining layer (120) disposed between the pixel electrodes; the wiring layer (130) contacting and overlapping respective portions of the first opposite electrode (231) and the second opposite electrode (232).
    • 一种显示装置,包括:衬底(100); 设置在基板上的第一像素电极(211) 设置在基板上的第二像素电极(212) 设置在所述基板上的像素限定层(120),所述像素限定层包括:设置在所述像素电极之间的部分; 以及分别与像素电极重叠的开口; 在所述第一像素电极上的第一中间层(221),所述第一中间层包括第一发射层; 在所述第二像素电极上的第二中间层(222),所述第二中间层包括与所述第一发射层间隔开的第二发射层; 在第一中间层上的第一相对电极(231) 在所述第二中间层上的第二相对电极(232),所述第二相对电极与所述第一相对电极间隔开; 以及布置在像素电极之间的部分像素限定层(120)的布线层(130) 所述布线层(130)接触并重叠所述第一相对电极(231)和所述第二相对电极(232)的相应部分。
    • 6. 发明公开
    • DISPLAY DEVICE
    • EP3223283A3
    • 2018-02-21
    • EP17168951.6
    • 2007-09-11
    • Semiconductor Energy Laboratory Co., Ltd.
    • Umezaki, AtsushiMiyake, Hiroyuki
    • G11C19/28G09G3/36
    • H01L27/124G09G3/2092G09G3/3266G09G3/3674G09G3/3677G09G2300/0809G09G2310/0205G09G2310/0248G09G2310/0286G09G2310/0289G09G2310/0291G09G2310/061G09G2320/0646G09G2320/0666G11C19/28H01L27/0207H01L27/1222H01L27/1225
    • A semiconductor device comprising: a first transistor; a second transistor; a third transistor; a fourth transistor; a fifth transistor; a sixth transistor; a seventh transistor; an eighth transistor; and a ninth transistor, wherein one of a source and a drain of the first transistor is directly connected to a first wiring, wherein the other of the source and the drain of the first transistor is directly connected to a second wiring, wherein one of a source and a drain of the second transistor is directly connected to a gate of the first transistor, wherein a gate of the second transistor is directly connected to a third wiring, wherein one of a source and a drain of the third transistor is directly connected to a fourth wiring, wherein the other of the source and the drain of the third transistor is directly connected to the gate of the first transistor, wherein one of a source and a drain of the fourth transistor is directly connected to the fourth wiring, wherein the other of the source and the drain of the fourth transistor is directly connected to the gate of the first transistor, wherein a gate of the fourth transistor is directly connected to a fifth wiring, wherein one of a source and a drain of the fifth transistor is directly connected to the fourth wiring, wherein the other of the source and the drain of the fifth transistor is directly connected to a gate of the third transistor, wherein a gate of the fifth transistor is directly connected to the gate of the first transistor, wherein one of a source and a drain of the sixth transistor is directly connected to a sixth wiring, wherein the other of the source and the drain of the sixth transistor is directly connected to the gate of the third transistor, wherein a gate of the sixth transistor is directly connected to the sixth wiring, wherein one of a source and a drain of the seventh transistor is directly connected to the sixth wiring, wherein the other of the source and the drain of the seventh transistor is directly connected to the gate of the third transistor. wherein one of a source and a drain of the eighth transistor is directly connected to a seventh wiring, wherein the other of the source and the drain of the eighth transistor is directly connected to the gate of the third transistor, wherein one of a source and a drain of the ninth transistor is directly connected to the seventh wiring, wherein the other of the source and the drain of the ninth transistor is directly connected to the gate of the third transistor, and wherein a gate of the ninth transistor is directly connected to the seventh wiring.
    • 7. 发明公开
    • CONTROL SUBUNIT, SHIFT REGISTER UNITS, SHIFT REGISTER, GRID DRIVE CIRCUIT AND DISPLAY DEVICE
    • 控制子单元,移位寄存器单元,移位寄存器,网格驱动电路和显示设备
    • EP3279887A1
    • 2018-02-07
    • EP15837171.6
    • 2015-08-21
    • BOE Technology Group Co., Ltd.
    • LI, Quanhu
    • G09G3/20
    • G09G3/2092G09G3/20G09G3/3266G09G3/3677G09G2300/0809G09G2310/0286G11C19/28
    • A control sub-unit (100), a shift register unit (201, 202 ... 20N), a shift register, a gate driving circuit and a display apparatus. The control sub-unit (100) comprises a low level input terminal (VGL), a selection module and N sets of nodes (Q1', QB1', Q2', QB2' ......QN', QBN'), each set of nodes (Q1', QB1', Q2', QB2' ......QN', QBN') comprises a first control node (Q1', Q2',......QN') and a second control node (QB1', QB2' ......QBN'), when the first control node (Q1') in one set of nodes (Q1', QB1') among the N sets of nodes is at a high level and the second control node (QB1') in said one set of nodes (Q1', QB1') is at a low level, the selection module connects the second control nodes (QB2' ......QBN') of the other N-1 sets of nodes (Q2', QB2' ......QN', QBN') to the low level input terminal, such that the first control nodes (Q2',......QN') and the second control nodes (QB2' ......QBN') in the other N-1 sets of nodes (Q2', QB2' ......QN', QBN') are all at the low level, wherein N is a positive integer larger than 1. Design of a narrow bezel of a display panel can be achieved.
    • 控制子单元(100),移位寄存器单元(201,202 ... 20N),移位寄存器,栅极驱动电路和显示装置。 控制子单元(100)包括低电平输入端(VGL),选择模块和N组节点(Q1',QB1',Q2',QB2'...... QN',QBN') ,每组节点(Q1',QB1',Q2',QB2'...... QN',QBN')包括第一控制节点(Q1',Q2',...... QN') 和第二控制节点(QB1',QB2'...... QBN'),当N组节点中的一组节点(Q1',QB1')中的第一控制节点(Q1')处于 所述一组节点(Q1',QB1')中的第二控制节点(QB1')处于低电平,所述选择模块将所述第二控制节点(QB2'...... QBN' )的其他N-1组节点(Q2',QB2'...... QN',QBN')输出到低电平输入端,使得第一控制节点(Q2',..., (Q2',QB2'...... QN',QBN')中的第二控制节点(QB2'...... QBN')全部是全部 处于低电平,其中N是大于1的正整数。可以实现显示面板的窄边框的设计。