专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明公开

EP1768173A1 METHOD FOR EVALUATING SOI WAFER 审中-公开
标题翻译： VERFAHREN ZUM BEWERTEN EINES SOI-WAFERS
公开(公告)号：EP1768173A1
公开(公告)日：2007-03-28
申请号：EP05745964.6
申请日：2005-05-31
申请人： SHIN-ETSU HANDOTAI COMPANY LIMITED
发明人： OHTSUKI, Tsuyoshi c/o Isobe R & D Center , SATO, Hideki c/o Isobe R & D Center
IPC分类号： H01L21/66
CPC分类号： G01R31/2648 , G01R31/2898
摘要： The present invention is a method for evaluating an SOI wafer by using a mercury probe, comprising at least steps of, subjecting the SOI wafer to a hydrofluoric acid cleaning treatment and thereby to remove a native oxide film formed in a surface of the SOI wafer, next subjecting the native oxide film-removed SOI wafer to a treatment for stabilizing charge state, then contacting the charge-state stabilizing-treated SOI wafer with the mercury probe, and thereby evaluating the SOI wafer. Thereby, there can be provided an evaluation method in which a large-scale apparatus and multiple steps such as a photolithography process are not required and by which an electric characteristic of an SOI wafer can be measured simply and high-precisely in a short time and operation rate of measurement apparatus is improved and thereby the SOI wafer can be effectively evaluated.
摘要翻译：本发明是一种通过使用水银探针来评估SOI晶片的方法，至少包括以下步骤：对SOI晶片进行氢氟酸清洗处理，从而除去在SOI晶片的表面形成的自然氧化膜，接下来对自然氧化物膜去除的SOI晶片进行用于稳定电荷状态的处理，然后使电荷状态稳定处理的SOI晶片与汞探针接触，从而评估SOI晶片。因此，可以提供一种评估方法，其中不需要诸如光刻工艺的大规模装置和多个步骤，并且可以在短时间内简单且高精度地测量SOI晶片的电特性，提高了测量装置的操作率，从而可以有效地评估SOI晶片。

2. 发明公开

EP2910960A1 PROCÉDÉ ET DISPOSITIF DE MISE SOUS CONTRAINTE THERMIQUE ET DE RAYONNEMENT D'UN CIRCUIT INTÉGRÉ 审中-公开
标题翻译：方法和设备的集成电路的热量和辐射暴露
公开(公告)号：EP2910960A1
公开(公告)日：2015-08-26
申请号：EP15160816.3
申请日：2011-04-19
申请人： Airbus Group SAS , Airbus Defence and Space SAS
发明人： Moliere, Florian , Morand, Sébastien , Douin, Alexandre , Salvaterra, Gérard , Binois, Christian , Peyre, Daniel
IPC分类号： G01R31/28 , H01L23/34
CPC分类号： G01R31/2863 , G01R31/2874 , G01R31/2898 , G01R31/311 , H01L2224/48091 , H01L2224/48247 , H01L2924/00014
摘要： La présente invention concerne un dispositif (3) de mise sous contrainte d'un circuit intégré (1) comportant une puce électronique (10) couplée thermiquement à un dissipateur thermique (124) accessible depuis l'extérieur d'un boîtier (12) à l'intérieur duquel ladite puce électronique est montée, le dispositif comportant une source (30) de contrainte thermique et une source (34) de contrainte de rayonnement. Le dispositif comporte en outre un organe (32) de couplage, thermiquement conducteur, destiné à être couplé thermiquement à la source (30) de contrainte thermique et à une partie accessible du dissipateur thermique (124) lors de la mise sous contrainte du circuit intégré (1), l'organe (32) de couplage étant de géométrie adaptée à préserver un accès optique au dissipateur thermique (124) dans lequel une ouverture doit être réalisée pour assurer un accès optique à une face (102) de la puce électronique (10) pour la mise sous contrainte de rayonnement.
摘要翻译：公开的是用于强调在包括在电子芯片（10）的集成电路（1），特别是（2）的装置安装在一个壳体（12），该装置包括热应力的来源（20）。因此，该设备（2）包括一热传导耦合部件（22），设计成被热耦合到热应力的应力操作期间源（20）。联接构件（22）包括端部（220）的几何形状适合于被引入到与预定义的几何形状的光圈，在所述集成电路的所述壳体（12），以进行（1）以热耦合的耦合为此（220）与所述电子芯片（10）的一个面（102）的面（222）。

3. 发明公开

EP2764376A1 A METHOD TO DIFFERENTIAL P-CHANNEL OR N-CHANNEL DEVICES BASED ON DIFFERENT ETCHING RATES. 有权
标题翻译： METHOD FOR分化P沟道或N沟道器件基于不同的蚀刻速率
公开(公告)号：EP2764376A1
公开(公告)日：2014-08-13
申请号：EP11873517.4
申请日：2011-09-27
申请人： CHIPWORKS, INCORPORATED
发明人： KLIBANOV, Lev , CAMPBELL, Jeffrey , SZKARLAT, Robert
IPC分类号： G01R31/28 , G01R31/26 , G01R31/307
CPC分类号： G01R31/307 , G01R31/2898
摘要： A method for determining if a device on a pre-existing CMOS integrated circuit is a p-channel device or an n-channel device. The method comprises etching the contact etch stop layer (CESL) which occurs at different rates on the two different CESL types thus allowing the device type to be determined by examining how much non-etched material is left.

4. 发明公开

EP2561373A1 PROCÉDÉS ET DISPOSITIFS DE MISE SOUS CONTRAINTE D'UN CIRCUIT INTÉGRÉ 失效转让
标题翻译： VERFAHREN UNDGERÄTZUR BELASTUNG EINER INTEGRIERTE SCHALTUNG
公开(公告)号：EP2561373A1
公开(公告)日：2013-02-27
申请号：EP11715703.2
申请日：2011-04-19
申请人： European Aeronautic Defence And Space Company Eads France , Astrium SAS
发明人： MOLIERE, Florian , MORAND, Sébastien , DOUIN, Alexandre , SALVATERRA, Gérard , BINOIS, Christian , PEYRE, Daniel
IPC分类号： G01R31/28 , H01L23/34
CPC分类号： G01R31/2863 , G01R31/2874 , G01R31/2898 , G01R31/311 , H01L2224/48091 , H01L2224/48247 , H01L2924/00014
摘要： The subject of the present invention is in particular a device (2) for stressing an integrated circuit (1) comprising an electronic chip (10) mounted in a package (12), said device comprising a source (20) of thermal stress. The device (2) also comprises a thermally conductive coupling member (22) intended to be thermally coupled to the source (20) of thermal stress during the stressing operation. The coupling member (22) comprises an end (220) having a geometry suited to introduction into an aperture having a preset geometry, which is to be produced in the package (12) of the integrated circuit (1) so as to thermally couple a coupling face (222) of this end (220) with a face (102) of the electronic chip (10).
摘要翻译：特别地公开了一种用于对包含安装在壳体（12）中的电子芯片（10）的集成电路（1）进行加压的装置（2），该装置包括热应力源（20）。装置（2）还包括导热联接构件（22），其被设计成在应力操作期间热耦合到热应力源（20）。联接构件（22）包括其几何形状适于被引入具有预定几何形状的孔中的端部（220），以在集成电路（1）的壳体（12）中形成，以便将耦合该端部（220）的面（222）与电子芯片（10）的面（102）相连。

5. 发明公开

EP1574866A1 INSPECTION METHOD AND INSPECTION EQUIPMENT 有权
标题翻译： UNTERSUCHUNGSVERFAHRENUNTERSUCHUNGSGERÄT
公开(公告)号：EP1574866A1
公开(公告)日：2005-09-14
申请号：EP03777392.6
申请日：2003-12-09
申请人： TOKYO ELECTRON LIMITED
发明人： SHINOZAKI, Dai, c/o TOKYO ELECTRON AT LIMITED , KOMATSU, Shigekazu, c/o TOKYO ELECTRON AT LIMITED
IPC分类号： G01R31/28
CPC分类号： G01R31/2886 , G01R31/2898 , G01R31/3161 , G01R31/31926
摘要： In an inspection method according to the invention, a plurality of drivers 21 incorporated in a tester 20 apply a fritting voltage to respective electrodes P via first probe pins 11A included in pairs of first and second probe pins 11A and 11B and connected to the respective drivers.
摘要翻译：在根据本发明的检查方法中，结合在测试器20中的多个驱动器21通过包括在成对的第一和第二探针11A和11B中的第一探针17来对各个电极P施加烧结电压，并连接到相应的驱动器。

6. 发明公开

EP2972430A4 CONFIGURABLE VERTICAL INTEGRATION 无效
标题翻译：可配置的垂直整合
公开(公告)号：EP2972430A4
公开(公告)日：2016-11-30
申请号：EP14774445
申请日：2014-03-13
申请人： LEEDY GLENN J
发明人： LEEDY GLENN J
IPC分类号： G01R31/317 , G01R31/28 , G01R31/3185 , G11C29/18 , H01L21/66 , H01L25/065
CPC分类号： G01R31/2851 , G01R31/2894 , G01R31/2898 , G01R31/318513 , G11C29/18 , H01L22/14 , H01L22/20 , H01L22/22 , H01L25/0657 , H01L2924/0002 , H01L2924/00
摘要： The Configurable Vertical Integration [CVI] invention pertains to methods and apparatus for the enhancement of yields of 3D or stacked integrated circuits and herein referred to as a CVI Integrated Circuit [CVI IC]. The CVI methods require no testing of circuit layer components prior to their fabrication as part of a 3D integrated circuit. The CVI invention uses active circuitry to configure the CVI IC as a means to isolate or prevent the use of defective circuitry. CVI circuit configuration method can be predominately described as a large grain method.
摘要翻译：可配置垂直整合[CVI]发明涉及用于增强3D或堆叠集成电路的产量的方法和装置，并且在本文中称为CVI集成电路[CVI IC]。作为3D集成电路的一部分，CVI方法在其制造之前不需要对电路层组件进行测试。 CVI发明使用有源电路来配置CVI IC作为隔离或防止使用有缺陷的电路的手段。 CVI电路配置方法主要被描述为大粒度法。

7. 发明公开

EP2904633A1 MULTIDIMENSIONAL STRUCTURAL ACCESS 有权
标题翻译：多维结构获得途径
公开(公告)号：EP2904633A1
公开(公告)日：2015-08-12
申请号：EP13843585.4
申请日：2013-10-04
申请人： FEI Company
发明人： BLACKWOOD, Jeffrey , LEE, Sang Hoon , SCHMIDT, Michael , STONE, Stacey , HOLLAND, Karey
IPC分类号： H01L21/66
CPC分类号： G01R31/2653 , G01N1/286 , G01N1/32 , G01R31/2808 , G01R31/2898 , G01R31/307 , G01R31/312 , H01J37/153 , H01J37/3005 , H01J2237/208 , H01J2237/24564 , H01J2237/2817 , H01J2237/31749 , H01L22/14 , H01L2924/0002 , H01L2924/00
摘要： Multiple planes within the sample are exposed from a single perspective for contact by an electrical probe. The sample can be milled at a non-orthogonal angle to expose different layers as sloped surfaces. The sloped edges of multiple, parallel conductor planes provide access to the multiple levels from above. The planes can be accessed, for example, for contacting with an electrical probe for applying or sensing a voltage. The level of an exposed layer to be contacted can be identified, for example, by counting down the exposed layers from the sample surface, since the non-orthogonal mill makes all layers visible from above. Alternatively, the sample can be milled orthogonally to the surface, and then tilted and/or rotated to provide access to multiple levels of the device. The milling is preferably performed away from the region of interest, to provide electrical access to the region while minimizing damage to the region.

8. 发明公开

EP2764376A4 A METHOD TO DIFFERENTIAL P-CHANNEL OR N-CHANNEL DEVICES BASED ON DIFFERENT ETCHING RATES. 有权
标题翻译：基于不同的蚀刻速率METHOD FOR分化P-通道或N沟道器件
公开(公告)号：EP2764376A4
公开(公告)日：2015-06-17
申请号：EP11873517
申请日：2011-09-27
申请人： CHIPWORKS INC
发明人： KLIBANOV LEV , CAMPBELL JEFFREY , SZKARLAT ROBERT
IPC分类号： G01R31/28 , G01R31/26 , G01R31/307
CPC分类号： G01R31/307 , G01R31/2898

9. 发明公开

EP1780765A3 Stage assembly, particle-optical apparatus comprising such a stage assembly, and method of treating a sample in such an apparatus 有权
标题翻译：级装置，具有用于在这样的设备中处理的样品这样的装置和方法粒子光学设备
公开(公告)号：EP1780765A3
公开(公告)日：2009-04-08
申请号：EP06123224.5
申请日：2006-10-31
申请人： FEI COMPANY
发明人： Tappel, Hendrik , Hees. van, Ian , Lankers, Danny , Giannuzzi, Lucille , Veen, van, Gerard , Young, Richard
IPC分类号： H01J37/20 , H01L21/68 , H01J37/30
CPC分类号： H01L21/68 , G01R31/2898 , H01J37/20 , H01J37/3005 , H01J37/3056 , H01J2237/201 , H01J2237/202 , H01J2237/20207 , H01J2237/20214 , H01J2237/20221 , H01J2237/20242 , H01L21/68764
摘要： A particle-optical apparatus comprising:
- A first source, for generating a first irradiating beam along a first axis;
- A second source, for generating a second irradiating beam along a second axis that intersects the first axis at a beam intersection point, the first and second axes defining a beam plane,
- A stage assembly (3) for positioning a sample in the vicinity of the beam intersection point, provided with:

- A sample table to which the sample can be mounted;
- A set of actuators, arranged so as to effect translation of the sample table along directions substantially parallel to an X-axis perpendicular to the beam plane, a Y-axis parallel to the beam plane, and a Z-axis parallel to the beam plane, said X-axis, Y-axis and Z-axis being mutually orthogonal and passing through the beam intersection point,

wherein the set of actuators is further arranged to effect:
- rotation of the sample table about a rotation axis substantially parallel to the Z-axis, and;
- rotation of the sample table about a flip axis substantially perpendicular to the Z-axis,

whereby the flip axis can itself be rotated about the rotation axis.

10. 发明公开

EP1726968A2 A method for local wafer thinning and reinforcement 审中-公开
标题翻译： Verfahren zur lokalenWaferdünnungund-verstärkung
公开(公告)号：EP1726968A2
公开(公告)日：2006-11-29
申请号：EP06010975.8
申请日：2006-05-29
申请人： CREDENCE SYSTEMS CORPORATION
发明人： Portune, Richard A.
IPC分类号： G01R31/28 , H01L21/02 , G01N1/32
CPC分类号： G01N1/32 , G01R31/2898 , Y10S438/977
摘要： A method is provided for preparing a semiconductor wafer (500) for testing. The method includes selecting a die (525) to be tested; measuring a diagonal of the die; thinning an area (550) over the die extending beyond the scribe lines (520a,520b), the thinned area may be a circular area having a diameter that is larger than the measured diagonal; providing an insert (560) inside the thinned area; and providing an adhesive (580) on the peripheral area of the insert so as not to obscure the optical path to the die. The insert (560) is advantageously made of an undoped silicon.
摘要翻译：提供了一种用于制备用于测试的半导体晶片（500）的方法。该方法包括选择待测试的管芯（525）; 测量模具的对角线; 使在模具上方延伸超过划线（520a，520b）的区域（550）变薄，所述变薄区域可以是直径大于测量对角线的圆形区域; 在所述减薄区域内提供插入件（560）; 以及在所述插入件的周边区域上提供粘合剂（580），以便不会模糊到所述模具的光路。插入件（560）有利地由未掺杂的硅制成。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式