专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明公开

EP2511721A3 Monitoring the low cycle fatigue of ruggedized avionics electronics 有权转让
标题翻译：监控耐用航空电子设备的低周疲劳
公开(公告)号：EP2511721A3
公开(公告)日：2017-10-18
申请号：EP12162778.0
申请日：2012-03-30
申请人： Hamilton Sundstrand Corporation
发明人： Morgana, Edward R. , Roy, Kevin P.
IPC分类号： G01R31/28 , G01R31/04 , G01R31/00
CPC分类号： G01R31/2849 , G01R31/008 , G01R31/048 , G01R31/2856 , G01R31/2872
摘要： A health monitoring system (14) for monitoring the health of an electronic system (10). The health monitoring system includes an analog-to-digital converter (22), and a monitoring circuit (24) within the electronic system. The monitoring circuit includes fatigue life characterized electrical components (26, 28, 30) representative of electrical components (12) comprising the balance of the electronic system. The fatigue life characterized electrical components are employed solely to monitor the health of the electronic system. The monitoring circuit output (20) is electrically connected to the analog-to-digital converter (22).
摘要翻译：一种用于监视电子系统（10）的健康的健康监视系统（14）。健康监测系统包括模数转换器（22）和电子系统内的监测电路（24）。监控电路包括表征包括电子系统的其余部分的电气部件（12）的疲劳寿命特征化电气部件（26,28,30）。以疲劳寿命为特征的电子元件仅用于监测电子系统的健康状况。监控电路输出（20）电连接到模数转换器（22）。

2. 发明公开

EP1882955A1 Fault Detection Apparatus For Surface Mount Package 审中-公开
标题翻译： Gerht zur Fehlerermittlung beioberflächenmontiertenGehäusen
公开(公告)号：EP1882955A1
公开(公告)日：2008-01-30
申请号：EP06118127.7
申请日：2006-07-28
申请人： Research In Motion Limited
发明人： Sheeran, John
IPC分类号： G01R31/04
CPC分类号： G01R31/048
摘要： A fault detection apparatus (60) for surface mount packages is provided. The apparatus can include a retainer for releasably securing a circuit board (38) such as a printed circuit board having an electrical component mounted thereon via a ball grid array surface mount package. When mounted within the apparatus, a test signal is applied to the electrical component. The apparatus includes a mechanical actuator, such as a solenoid (68), for applying a reciprocating force to the circuit board (38). The reciprocating force can disturb a defect (54) in the ball grid array manifesting as a mechanically unreliable connection at one of the balls where an electrically intermittent connection is occurring. By disturbing the mechanically unreliable connection, the electrically intermittent connection can be caused to fail altogether and thereby reveal the defect as a test signal is carried through the printed circuit board.
摘要翻译：提供了一种用于表面贴装封装的故障检测装置（60）。该装置可以包括用于可释放地固定电路板（38）的保持器，例如经由球栅阵列表面安装封装安装在其上的电气部件的印刷电路板。当安装在设备内时，将测试信号施加到电气部件。该装置包括用于向电路板（38）施加往复力的机械致动器，例如螺线管（68）。往复力可以扰乱球栅阵列中的缺陷（54），其表现为在发生电间断连接的球之一中机械不可靠的连接。通过扰乱机械不可靠的连接，可以使电气间断连接完全失效，从而在通过印刷电路板传送测试信号时显露缺陷。

3. 发明公开

EP1679520A1 Printed circuit board inspecting apparatus, inspection logic setting method, and inspection logic setting apparatus 审中-公开
标题翻译：一种用于检查印刷电路板，设置验证逻辑的方法和装置，用于调整所述验证逻辑
公开(公告)号：EP1679520A1
公开(公告)日：2006-07-12
申请号：EP06100242.4
申请日：2006-01-11
申请人： OMRON CORPORATION
发明人： MORIYA, Toshihiro , WADA, Hirotaka , ONISHI, Takako , SHIMIZU, Atsushi , NAKAJIMA, Akira
IPC分类号： G01R31/04 , G01N21/956
CPC分类号： G01R31/048 , G01N21/95684
摘要： A technology is provided for automatically producing an inspection logic to be used in the action of inspecting a PC board. An inspection logic setting apparatus (2) is arranged for acquiring a plurality of first images of components to be detected by the inspection and a plurality of second images of components to be rejected by the inspection, dividing each of said plurality of first and second images into the plurality of blocks, calculating a color distance between said plurality of first images and said plurality of second images in said each block, selecting one or more blocks from said plurality of blocks which are relatively greater in the color distance, and assigning said selected block(s) to the area condition.
摘要翻译：甲技术提供了一种用于在检查逻辑自动产生在检查PC板的作用而被使用。检查逻辑设定装置（2）被布置为获取部件的第一图像生成多个由检查和的部件的第二图像的多元性可检测到由检验被拒绝，将每个第一和第二图像的所述多个成块的多元性，计算第一图像的所述多个和在所述第二图像中的每个块，从块哪些是在颜色距离相对较大的所述多个选择一个或多个块，并分配所述的多个之间的色距所述选择的块（或多个）的面积的条件。

4. 发明授权

EP0892274B1 A system and method for easily inspecting a bonded state of a BGA/CSP type electronic part to a board 失效
标题翻译：系统和方法，用于容易地检查电子BGA / CSP部件和支撑板之间的连接
公开(公告)号：EP0892274B1
公开(公告)日：2002-08-21
申请号：EP98109865.0
申请日：1998-05-29
申请人： SHARP KABUSHIKI KAISHA
发明人： Ojiri, Hirofumi , Yasumoto, Takashi
IPC分类号： G01R31/28 , G01R31/04
CPC分类号： G01R31/2853 , G01R31/048 , H05K1/0268

5. 发明公开

EP0892274A3 A system and method for easily inspecting a bonded state of a BGA/CSP type electronic part to a board 失效
标题翻译：系统和方法，用于容易地检查电子BGA / CSP部件和支撑板之间的连接
公开(公告)号：EP0892274A3
公开(公告)日：2000-08-02
申请号：EP98109865.0
申请日：1998-05-29
申请人： SHARP KABUSHIKI KAISHA
发明人： Ojiri, Hirofumi , Yasumoto, Takashi
IPC分类号： G01R31/28 , G01R31/04
CPC分类号： G01R31/2853 , G01R31/048 , H05K1/0268
摘要： In a BGA/CSP type electronic part (1) having a matrix-shaped array of solder pads on its back surface, the solder pads at first two corners on one side of the array are connected with each other by an inner pattern wire (3a), and the solder pads at the other, second two corners on the opposite side are also connected with each other by an inner pattern wire (3b). In a printed wiring board (4) having a matrix-shaped array of connection pads on its top surface, pattern wires (6a, 6b, 6c, 6d) are extended from the connection pads at four corners of the connection pad array to form test lands (7a, 7b, 7c, 7d). Further, the connection pads, at two of the corners, to be bonded with the solder pads at one of the first two corners and at one of the second two corners confronting the one of the first two corners are connected with each other by a pattern wire (6i). Thus, after the BGA/CSP type electronic part is mounted in position on the printed wiring board, the state of the connection between the BGA/CSP type electronic part and the printed wiring board can be confirmed by checking the state of continuity between the test lands (7a, 7c) connected with the connection pads at the other two corners of the connection pad array.

6. 发明授权

EP0105078B1 Fiber optic scanning system for laser/thermal inspection 失效
标题翻译：用于激光/热检测的光纤扫描系统
公开(公告)号：EP0105078B1
公开(公告)日：1989-03-22
申请号：EP83103993.8
申请日：1983-04-23
申请人： VANZETTI SYSTEMS, INC.
发明人： Vanzetti, Riccardo , Dostoomian, Ashod S. , Traub, Alan C.
IPC分类号： G01N25/72
CPC分类号： G01N25/72 , G01R31/048 , G01R31/309

7. 发明公开

EP2095143A1 METHOD AND CIRCUIT FOR LOW-POWER DETECTION OF SOLDER-JOINT NETWORK FAILURES IN DIGITAL ELECTRONIC PACKAGES 审中-公开
标题翻译：方法与电路低功率检测焊点网络故障在数字ELEKTRONIKKAPSELUNGEN
公开(公告)号：EP2095143A1
公开(公告)日：2009-09-02
申请号：EP07874147.7
申请日：2007-11-23
申请人： Ridgetop Group, Inc.
发明人： MARIANI, Giorgio , HOFMEISTER, James, P. , JUDKINS, Justin, B.
IPC分类号： G01R31/26 , H02H9/04 , H05B1/00
CPC分类号： G01R31/048
摘要： A low power circuit 100 and method for detects in-situ failures or precursors to failures in solder- joint networks 91 on actual operational devices and packages in the field. An amplifying detector 102 such as provided by a common- gate transistor sources current to a monitor network 90 to generate a signal voltage and a reference voltage that is sensitive to the low voltage applied to the other side of the network. Generation of this self-adjusting reference voltage makes the comparator 104 insensitive to the network low-voltage. Additional power savings and performance gains can be provided with the addition of a differential amplifier to set a fixed bias point aηd a level shifter to cancel noise. The detected failure or precursor of a selected monitor solder- joint network (s) 90 is an indicator of the integrity of other operational solder- joint networks 91 in the package, on the PWB or between PWBs.

8. 发明公开

EP2031413A2 High-sensitive resistance measuring device and monitoring method of solder bump 审中-公开
标题翻译： Hochempfindliche Widerstandsmessvorrichtung und KontrollverfahrenfürLötkugeln
公开(公告)号：EP2031413A2
公开(公告)日：2009-03-04
申请号：EP08156414.8
申请日：2008-05-19
申请人： Fujitsu Limited
发明人： Nakamura, Naoaki c/o FUJITSU ADVANCED TECHNOLOGIES LIMITED
IPC分类号： G01R27/14
CPC分类号： G01R27/14 , G01R31/048 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/15311 , H01L2924/00
摘要： According to an aspect of an embodiment, a highly-sensitive resistance measuring device of solder bumps (20-11,20-12,20-13) comprises a resistance variation detection unit which detects a differential voltage (ΔV=V1-V2), which is obtained by subtracting a second voltage (V2) generated in a reference bump connection unit by a constant current (I) from a second constant current source from a first voltage (V1) generated in a monitored bump connection unit by the constant current (I) from a first constant current source, as a resistance variation voltage representing a resistance variation (ΔR) of the monitored bump connection unit.
摘要翻译：根据实施例的一个方面，焊料凸块（20-11,20-12,20-13）的高灵敏度电阻测量装置包括电阻变化检测单元，其检测差分电压（“V = V1-V2”），，其通过用来自第二恒定电流源的恒定电流（I）从在监测的凸块连接单元中产生的第一电压（V1）中的恒定电流减去在参考凸块连接单元中产生的第二电压（V2）（I）作为表示所监视的凸块连接单元的电阻变化（“R”）的电阻变化电压。

9. 发明公开

EP1949118A1 METHOD, CIRCUIT BOARD AND TEST APPARATUS FOR TESTING SOLDER JOINTS 审中-公开
标题翻译：方法，电路板和试验装置测试焊点
公开(公告)号：EP1949118A1
公开(公告)日：2008-07-30
申请号：EP06794096.5
申请日：2006-10-02
申请人： Tuominen, Aulis , Tuollo, Ikka
发明人： Tuominen, Aulis , Tuollo, Ikka
IPC分类号： G01R31/04
CPC分类号： G01R31/048 , G01R1/0408 , G01R31/2837
摘要： The invention relates to a method for testing the reliability of solder joints of electric components (115, 119). Electric components are arranged through solder joints between the first and the second pads arranged in pairs. In a method an electric signal is fed into the electric signal input area (107), and the electric signal is conducted by an electric conductor (105, 130) to the first pad (103), the electric signal is measured at the measurement area (108) which is arranged by electric conductors (106, 125) in series with the second pad (104). According to the invention one or more pad pair groups are formed from the pad pairs, whereby in the method an electric signal is conducted from the electric signal input area (107) simultaneously to two or more first pads (103) of one pad pair group, which two or more first pads are connected in series for conducting electric current. Furthermore, the electric signal is measured at one or more measurement areas (108), each of which is arranged by electric conductors in series with one second pad (104) of one pad pair group. The invention relates further to a circuit board (100) and a test apparatus (500), which has a circuit board according to the invention.

10. 发明公开

EP1853931A4 METHOD AND CIRCUIT FOR THE DETECTION OF SOLDER-JOINT FAILURES IN A DIGITAL ELECTRONIC PACKAGE 审中-公开
标题翻译：方法与电路的数字式电子元件外壳体认LÖTNAHTFEHLERN
公开(公告)号：EP1853931A4
公开(公告)日：2008-04-16
申请号：EP06734539
申请日：2006-02-08
申请人： RIDGETOP GROUP INC
发明人： VERMEIRE BERT , HOFMEISTER JAMES , SPUHLER PHILIPP
IPC分类号： G01R1/073 , G01R31/28
CPC分类号： G01R31/048 , G01R31/2884 , G01R31/312
摘要： The solder-joint integrity of digital electronic packages, such as FPGAs (120) or microcontrollers that have internally connected input /output buffers (146a/b, 148a/b), is evaluated by applying a time-varying voltage through one or more solder- joint networks (153a) to charge a charge- storage component (156). Each network includes an I/O buffer (146a) on the die (138) in the package and a solder-joint connection (124), typically one or more such connections inside the package and between the package and a board. The time constant for charging the component is proportional to the resistance of the solder- joint network, hence the voltage measured across the charge-storage component is an indicator of the integrity of the solder-joint network.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式