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1. 发明公开

EP4393869A1 METHOD FOR WELDING SUBSTRATES AND WELDED SUBSTRATES 审中-实审
公开(公告)号：EP4393869A1
公开(公告)日：2024-07-03
申请号：EP22216975.7
申请日：2022-12-28
申请人： SCHOTT AG , SCHOTT Primoceler Oy
发明人： THOMAS, Jens Ulrich , MÄÄTTÄNEN, Antti , POLOJÄRVI, Ville , LAHTINEN, Ossi
IPC分类号： B81B7/00 , B81C1/00 , B23K26/20
CPC分类号： B81C1/00357 , C03B23/245 , B23K26/20 , B81C2203/011820130101 , B81C1/00904
摘要： The invention relates to a method for welding substrates comprising: bringing a first substrate and a second substrate in contact with each other such that a contact area between the two substrates is formed; introducing at least two outer weld lines extending next to each other within the contact area into the first and second substrates such that the first and second substrates are welded together by each of the outer weld lines and such that a dicing area is defined between the two outer weld lines; and introducing one or more inner weld lines extending between the two outer weld lines within the dicing area into at least one of the two substrates. The invention further relates to welded substrates and to singulated chips, in particular hermetically sealed enclosures.

2. 发明公开

EP1356511A1 USE OF PROTECTIVE CAPS AS MASKS AT A WAFER SCALE 有权
标题翻译：帽口罩晶圆面积使用
公开(公告)号：EP1356511A1
公开(公告)日：2003-10-29
申请号：EP02729355.4
申请日：2002-01-08
申请人： Silverbrook Research Pty. Limited
发明人： SILVERBROOK, Kia
IPC分类号： H01L21/822 , H01L23/04
CPC分类号： B81C1/00333 , B29C33/0022 , B29C43/36 , B29C2035/0822 , B29C2043/503 , B81C1/00904 , B81C2201/034 , B81C2203/0109 , B81C2203/0127 , H01L21/4803 , H01L23/04 , H01L2924/0002 , H01L2924/16235 , H01L2924/00
摘要： Caps (156, 160) are bonded to one or both sides of a wafer (150) to overlay in plan view all or part of a microfabricated device or group of devices (152). One or more etches (164) are applied from the cap side to remove material and to separate the wafer (150) into discrete units.

3. 发明公开

EP1356511A4 USE OF PROTECTIVE CAPS AS MASKS AT A WAFER SCALE 有权
标题翻译： VERWENDUNG VON SCHUTZKAPPEN ALS MASKEN AUF WAFER-MASSSTAB
公开(公告)号：EP1356511A4
公开(公告)日：2006-06-07
申请号：EP02729355
申请日：2002-01-08
申请人： SILVERBROOK RES PTY LTD
发明人： SILVERBROOK KIA
IPC分类号： H01L21/301 , B29C35/08 , B29C43/36 , B81B7/00 , B81C1/00 , H01L21/48 , H01L23/02 , H01L23/04 , H01L21/822
CPC分类号： B81C1/00333 , B29C33/0022 , B29C43/36 , B29C2035/0822 , B29C2043/503 , B81C1/00904 , B81C2201/034 , B81C2203/0109 , B81C2203/0127 , H01L21/4803 , H01L23/04 , H01L2924/0002 , H01L2924/16235 , H01L2924/00
摘要： Caps (156, 160) are bonded to one or both sides of a wafer (150) to overlay in plan view all or part of a microfabricated device or group of devices (152). One or more etches (164) are applied from the cap side to remove material and to separate the wafer (150) into discrete units.
摘要翻译：在制造微机电系统（MEMS）装置的微细加工装置（152）中使用施加到晶片（150）的第一侧的保护帽（160）的方法。一个盖（160）分别覆盖每个微加工装置或组，使得相邻保护盖之间保持间隙。将一个或多个蚀刻施加到盖之间的间隙以移除材料并将晶片分离成单独的单元。

4. 发明公开

EP1111671A3 Verfahren zum Herstellen einer Halbleiteranordnung 有权
标题翻译：一种制造半导体器件的方法
公开(公告)号：EP1111671A3
公开(公告)日：2004-05-12
申请号：EP00127180.8
申请日：2000-12-12
申请人： Micronas GmbH
发明人： Igel, Günter, Dipl.-Ing.
IPC分类号： H01L21/78 , B81C1/00
CPC分类号： B81C1/00904 , B81C1/00896 , B81C2201/053 , H01L21/78 , H01L23/3171 , H01L2924/0002 , Y10S438/928 , H01L2924/00
摘要： Ein Verfahren dient zum Herstellen einer Halbleiteranordnung (3), wobei insbesondere ein Wafer (1) mit einer Vielzahl von Chips (7) bildenden Halbleiteranordnungen hergestellt und der Wafer danach zerteilt und dadurch die Halbleiteranordnungen vereinzelt werden. Zumindest ein Bereich einer Waferseite wird während des Ätzens des übrigen Waferbereichs mittels einer Passivierungsschicht (9) abgedeckt. Nach dem Ätzen wird dann die Passivierungsschicht (9) entfernt. Zumindest in einem äußeren Randbereich des Wafers, gegebenenfalls zusätzlich im Verlauf der Wafer-Vorderseite, außerhalb der aktiven Chipfläche und insbesondere in den die jeweiligen Chipsysteme umgrenzenden Bereichen werden Haftzonen (8) für die Passivierungsschicht (9) geschaffen, die mit dem für die Passivierungsschicht verwendeten Material eine dichtende, insbesondere chemische Verbindung eingehen. Außerhalb der Haftzonen ist eine verminderte Haftfähigkeit vorhanden, so dass die Passivierungsschicht (9) zum Beispiel nach dem Rückseitenätzen in dem außerhalb der Haftzonen (8) liegenden Bereich mechanisch durch einen Flüssigkeitsstrom und/oder durch einen Gasstrom und/oder durch Ultraschallbeaufschlagung von der Waferoberfläche entfernt werden kann.

5. 发明公开

EP1358489A1 ACCELEROMETER PROTECTED BY CAPS APPLIED AT THE WAFER SCALE 有权
标题翻译： PROCESS加速度计通过对保护方式晶圆级APPLIED CAPS
公开(公告)号：EP1358489A1
公开(公告)日：2003-11-05
申请号：EP02729357.0
申请日：2002-01-08
申请人： Silverbrook Research Pty. Limited
发明人： SILVERBROOK, KIA,Silverbrook Research Pty Ltd
IPC分类号： G01P15/08 , H01L21/822 , H01L23/04
CPC分类号： H01L23/315 , B29C33/0022 , B29C43/36 , B29C2035/0822 , B29C2043/503 , B81B2201/0235 , B81B2207/056 , B81C1/00269 , B81C1/00333 , B81C1/00904 , B81C2201/034 , B81C2203/0127 , G01P1/023 , G01P15/0802 , H01L23/16 , H01L2224/48091 , H01L2224/48247 , H01L2224/48465 , H01L2924/10253 , H01L2924/15747 , H01L2924/181 , H01L2924/3011 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： An accelerometer chip (202) has a molded thermoplastic cap (210) applied on one surface to provide a cavity into which the cantilevered mass (204) of the accelerometer may move. An array of caps is applied to a wafer of accelerometer chips (202) before singulation of the wafer.

6. 发明公开

EP3093880A1 SILICON-ON-SAPPHIRE DEVICE WITH MINIMAL THERMAL STRAIN PRELOAD AND ENHANCED STABILITY AT HIGH TEMPERATURE 无效
标题翻译：含基本热膨胀负荷和改进的稳定性高温SOS DEVICE
公开(公告)号：EP3093880A1
公开(公告)日：2016-11-16
申请号：EP16163058.7
申请日：2016-03-30
申请人： Honeywell International Inc.
发明人： BROWN, Gregory C.
IPC分类号： H01L21/762 , B81B3/00
CPC分类号： B81B3/0078 , B81B3/004 , B81B2201/0264 , B81B2203/0127 , B81B2207/094 , B81C1/00904 , B81C2203/037 , G01L9/0055 , H01L21/76254 , H01L21/86
摘要： A silicon-on-sapphire chip with minimal thermal strain preload is provided. The chip includes a sapphire substrate having a first-sapphire surface and an opposing second-sapphire surface; and a silicon layer overlaying the first-sapphire surface. The silicon layer is formed by: creating a plurality of buried cavities in a plane within tens of microns from a first-silicon surface of a silicon wafer; laser fusing the first-silicon surface to the first-sapphire surface at room temperature to attach the silicon wafer to a sapphire wafer; and cleaving the silicon wafer along the plane including the plurality of buried cavities. A silicon-wafer layer is formed from the silicon material between the first-silicon surface and the plane of the plurality of buried cavities. The silicon-wafer layer and the sapphire wafer form a silicon-on-sapphire wafer. The silicon-on-sapphire chip is formed by dicing the silicon-on-sapphire wafer.
摘要翻译：本发明提供一种硅 - 蓝宝石上芯片具有最小的热应变的预载荷。该芯片包括具有第一蓝宝石表面和相对的第二蓝宝石表面的蓝宝石衬底; 和硅层覆盖所述第一蓝宝石表面。硅树脂层通过以下步骤形成：在几十从硅晶片的第一有机硅表面微米内的平面创建掩埋腔体的多元性; 激光熔接第一硅表面到第一表面的蓝宝石在室温下附着在硅晶片的蓝宝石晶片; 和切割沿平面包括掩埋空腔的多个硅晶片。甲硅晶片层从第一硅表面和埋入腔的多个平面之间的硅材料形成。硅晶片层和蓝宝石晶片形成硅 - 蓝宝石晶片。硅 - 蓝宝石上芯片通过切割硅 - 蓝宝石晶片形成。

7. 发明公开

EP1766663A4 METHODS FOR DEPOSITING, RELEASING AND PACKAGING MICRO-ELECTROMECHANICAL DEVICES ON WAFER SUBSTRATES 审中-公开
标题翻译：方法存款，自由和胶囊微机电装置ON晶片衬底
公开(公告)号：EP1766663A4
公开(公告)日：2012-03-21
申请号：EP03817376
申请日：2003-06-11
申请人： TEXAS INSTRUMENTS INC
发明人： PATEL SATYADEV , HUIBERS ANDREW , RICHARDS PETER , SHI HONGQIN , CHIANG STEVE , DUBOC ROBERT JR , GROBELNY THOMAS , DEHLINGER DIETRICH , SUN ANTHONY , CHEN HUNG NAN
IPC分类号： G02B26/08 , B81B3/00 , B81B7/00 , B81C1/00 , B81C3/00 , B81C99/00 , H01L21/301 , H01L21/60 , H01L23/02 , H01L23/22 , H01L23/24
CPC分类号： B81B7/0077 , B81B2201/042 , B81C1/00269 , B81C1/00904 , B81C2203/0118 , B82Y30/00 , G02B26/0833 , G02B26/0841 , H01L24/97 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01018 , H01L2924/01019 , H01L2924/0102 , H01L2924/01023 , H01L2924/01027 , H01L2924/01033 , H01L2924/01039 , H01L2924/01049 , H01L2924/01054 , H01L2924/01072 , H01L2924/01074 , H01L2924/01076 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/04953 , H01L2924/10329 , H01L2924/12036 , H01L2924/12042 , H01L2924/12044 , H01L2924/1461 , H01L2924/19041 , H01L2924/19042 , H01L2924/3025 , H01L2924/00
摘要： A projection system, a spatial light modulator, and a method for forming a MEMS device is disclosed. The spatial light modulator can have two substrates bonded together with one of the substrates comprising a micromirror array. The two substrates can be bonded at the wafer level after depositing a getter material andlor solid or liquid lubricant on one or both of the wafers. The wafers can be bonded together hermetically if desired, and the pressure between the two substrates can be below atmosphere.

8. 发明授权

EP1301432B1 METHOD OF FABRICATING DEVICES INCORPORATING MICROELECTROMECHANICAL SYSTEMS USING UV CURABLE TAPES 有权
标题翻译：用于生产微机电系统含有组分具有UV可固化波段中
公开(公告)号：EP1301432B1
公开(公告)日：2007-01-10
申请号：EP01927493.5
申请日：2001-05-02
申请人： Silverbrook Research Pty. Limited
发明人： SILVERBROOK, Kia, c/o Silverbrook Research Pty Ltd
IPC分类号： B81C1/00 , B41J2/16
CPC分类号： B81C1/00904 , H01L21/6835 , H01L21/6836 , H01L2221/68322 , H01L2221/68327 , H01L2221/6834 , H01L2221/68381 , Y10S438/977 , Y10T156/1052 , Y10T156/1064 , Y10T428/1495
摘要： A method of fabricating devices incorporating microelectromechanical systems (MEMS) using UV curable tapes includes providing a silicon substrate (12) with a MEMS layer (14) arranged on one side of the substrate (12). A first UV curable tape (22) is applied to the MEMS layer (14). At least one operation is performed on the substrate (14) via an opposed side of the substrate (14). A second UV curable tape (32) is applied to the opposed side of the substrate (14) and the first tape (22) is removed by exposing it to UV light. At least one operation is performed on the MEMS layer to form individual MEMS chips which are able to be removed individually from the second UV tape (32) by localised exposure of the tape (32) to UV light.

9. 发明公开

EP1301432A1 METHOD OF FABRICATING DEVICES INCORPORATING MICROELECTROMECHANICAL SYSTEMS USING UV CURABLE TAPES 有权
标题翻译：用于生产微机电系统含有组分具有UV可固化波段中
公开(公告)号：EP1301432A1
公开(公告)日：2003-04-16
申请号：EP01927493.5
申请日：2001-05-02
申请人： Silverbrook Research Pty. Limited
发明人： SILVERBROOK, Kia,c/o Silverbrook Research Pty Ltd
IPC分类号： B81C1/00 , B41J2/16
CPC分类号： B81C1/00904 , H01L21/6835 , H01L21/6836 , H01L2221/68322 , H01L2221/68327 , H01L2221/6834 , H01L2221/68381 , Y10S438/977 , Y10T156/1052 , Y10T156/1064 , Y10T428/1495
摘要： A method of fabricating devices incorporating microelectromechanical systems (MEMS) using UV curable tapes includes providing a silicon substrate (12) with a MEMS layer (14) arranged on one side of the substrate (12). A first UV curable tape (22) is applied to the MEMS layer (14). At least one operation is performed on the substrate (14) via an opposed side of the substrate (14). A second UV curable tape (32) is applied to the opposed side of the substrate (14) and the first tape (22) is removed by exposing it to UV light. At least one operation is performed on the MEMS layer to form individual MEMS chips which are able to be removed individually from the second UV tape (32) by localised exposure of the tape (32) to UV light.
摘要翻译：制造掺入微机电系统使用可UV固化的带（MEMS）器件的方法，包括：提供硅衬底12与设置在第一可UV固化的带22被施加到MEMS层14.在基片12的一侧上的MEMS层14 至少一个手术处于第二可UV固化的带32被施加到基底14和第一带22的相对侧是通过将其暴露于UV光中除去基片14的相对侧通过执行对基片14。至少一个工作在所述MEMS层上进行以形成单独的MEMS芯片，其能够由带32的局部暴露于UV光将被从所述第二独立UV带32移除。

10. 发明授权

EP1993948B1 MEMS DEVICE 有权转让
标题翻译： MEMS器件
公开(公告)号：EP1993948B1
公开(公告)日：2016-04-13
申请号：EP07705267.8
申请日：2007-02-23
申请人： Cirrus Logic International Semiconductor Ltd.
发明人： LAMING, Richard, Ian , TRAYNOR, Anthony
IPC分类号： G01L9/00 , H04R3/00 , H04R19/00 , H04R19/04
CPC分类号： B81C1/00158 , B81B3/0027 , B81B2201/0257 , B81C1/00246 , B81C1/00904 , B81C2201/056 , G01L9/0073 , H04R3/005 , H04R19/005 , H04R19/04

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