专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

EP0463374B1 Memory cell circuit and operation thereof 失效
标题翻译：存储单元电路和操作
公开(公告)号：EP0463374B1
公开(公告)日：1997-08-06
申请号：EP91108473.9
申请日：1991-05-24
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Mahant-Shetti, Shivaling S. , Harward, Mark G.
IPC分类号： G11C11/412
CPC分类号： G11C11/412

2. 发明授权

EP0446721B1 Distributed processing memory 失效
标题翻译：分布式处理存储器
公开(公告)号：EP0446721B1
公开(公告)日：2000-12-20
申请号：EP91103080.7
申请日：1991-03-01
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Mahant-Shetti, Shivaling S. , Smith, Derek J. , Pawate, Basavaraj I. , Doddington, George R. , Bean, Warren L. , Harward, Mark G. , Aton, Thomas J.
IPC分类号： G06F12/06 , G06F15/80
CPC分类号： G06F9/3879 , G06F12/0646 , G06F15/7821

3. 发明公开

EP0469393A3 Arithmetic and logic units 失效
标题翻译：算术和逻辑单元
公开(公告)号：EP0469393A3
公开(公告)日：1993-01-27
申请号：EP91111974.1
申请日：1991-07-17
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Mahant-Shetti, Shivaling S. , Swamy, Shobana
IPC分类号： G06F7/48 , G11C11/412
CPC分类号： G06F7/575 , G11C11/412
摘要： An arithmetic and logic unit implemented in a memory array is provided. The memory has a plurality of memory cells each with a memory storage element and each accessible via a word line and at least one bit line. The arithmetic and logic unit comprises a plurality of logic circuits coupled to the word and bit lines in place of the memory storage elements of certain memory cells. Each of the plurality of pull down logic circuits implements an arithmetic and/or logic function.

4. 发明公开

EP0493830A2 Memory cell circuit and array 失效
标题翻译： Speicherzelleschaltung和矩阵。
公开(公告)号：EP0493830A2
公开(公告)日：1992-07-08
申请号：EP91122374.1
申请日：1991-12-30
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Harward, Mark G. , Mahant-Shetti, Shivaling S. , Tigelaar, Howard
IPC分类号： G11C11/402 , G11C11/412
CPC分类号： G11C11/4023 , G11C11/412
摘要： An improved memory cell (118) is provided which may be incorporated into an array (202) of memory cells. Array (202) includes a first gate conductor region (224) and a second gate conductor region (238), wherein the first and second gate conductor regions are orthogonal to one another. Each one-half of the cell may include two series transistors connected to a cross-coupled trench transistor. Cross-coupling of the trench transistors is effected through the use of parallel local interconnect regions (256) and (258).
摘要翻译：提供了一种改进的存储单元（118），其可以并入到存储器单元的阵列（202）中。阵列（202）包括第一栅极导体区域（224）和第二栅极导体区域（238），其中第一和第二栅极导体区域彼此正交。单元的每一半可以包括连接到交叉耦合沟槽晶体管的两个串联晶体管。通过使用并联局部互连区域（256）和（258）来实现沟槽晶体管的交叉耦合。

5. 发明公开

EP0469393A2 Arithmetic and logic units 失效
标题翻译：。。。。
公开(公告)号：EP0469393A2
公开(公告)日：1992-02-05
申请号：EP91111974.1
申请日：1991-07-17
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Mahant-Shetti, Shivaling S. , Swamy, Shobana
IPC分类号： G06F7/48 , G11C11/412
CPC分类号： G06F7/575 , G11C11/412
摘要： An arithmetic and logic unit implemented in a memory array is provided. The memory has a plurality of memory cells each with a memory storage element and each accessible via a word line and at least one bit line. The arithmetic and logic unit comprises a plurality of logic circuits coupled to the word and bit lines in place of the memory storage elements of certain memory cells. Each of the plurality of pull down logic circuits implements an arithmetic and/or logic function.
摘要翻译：提供了一种在存储器阵列中实现的算术和逻辑单元。存储器具有多个存储器单元，每个存储器单元具有存储器存储元件，并且每个存储器单元可经由字线和至少一个位线访问。算术和逻辑单元包括耦合到字和位线的多个逻辑电路来代替某些存储器单元的存储器存储元件。多个下拉逻辑电路中的每一个实现算术和/或逻辑功能。

6. 发明公开

EP0463374A2 Memory cell circuit and operation thereof 失效
标题翻译： Speicherzellenschaltung und Betrieb。
公开(公告)号：EP0463374A2
公开(公告)日：1992-01-02
申请号：EP91108473.9
申请日：1991-05-24
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Mahant-Shetti, Shivaling S. , Harward, Mark G.
IPC分类号： G11C11/412
CPC分类号： G11C11/412
摘要： An improved memory cell 118 is provided utilizing transistor pairs 142, 144 and 160, 162 as dual purpose transistor pairs for the two modes of operation of the cell. During the first or non-access mode of operation, the transistor pairs operate as switched capacitive elements in order to provide an equivalent resistance between bit line 140 and first node 26 and inverted bit line 158 and second node 130. Control circuit 119 maintains bit lines 140 and inverted bit line 158 high during this non-access mode. During the second or access mode of operation, each transistor pair operates as a respective pass transistor for connecting bit line 140 to first node 126 and inverted bit line 158 to second node 130 so that data may be read from, or written to, the cross-coupled transistors 120 and 122.
摘要翻译：提供改进的存储单元118，利用晶体管对142,144和160,162作为用于单元的两种操作模式的双用途晶体管对。在第一或非访问操作模式期间，晶体管对作为开关电容元件工作，以便在位线140与第一节点26以及反相位线158和第二节点130之间提供等效电阻。控制电路119维持位线 140和反向位线158在该非接入模式期间为高。在第二或访问操作模式期间，每个晶体管对作为相应的传输晶体管工作，用于将位线140连接到第一节点126，并将反向位线158连接到第二节点130，使得数据可以被读取或写入十字耦合晶体管120和122

7. 发明授权

EP0469393B1 Static random access array including at least one arithmetic and logic unit 失效
标题翻译：静态随机存取存储器阵列，其中包含至少一个算术逻辑单元
公开(公告)号：EP0469393B1
公开(公告)日：1999-10-06
申请号：EP91111974.1
申请日：1991-07-17
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Mahant-Shetti, Shivaling S. , Swamy, Shobana
IPC分类号： G06F7/48 , G11C11/412
CPC分类号： G06F7/575 , G11C11/412

8. 发明授权

EP0564679B1 Gate array base cell 失效
标题翻译：门阵列基本单元
公开(公告)号：EP0564679B1
公开(公告)日：1997-12-10
申请号：EP92106062.0
申请日：1992-04-08
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Hashimoto, Mashashi , Mahant-Shetti, Shivaling S.
IPC分类号： H01L27/118
CPC分类号： H01L27/11807 , H01L21/8238

9. 发明公开

EP0647030A3 Integrated circuit devices 失效
标题翻译：集成电路装置。
公开(公告)号：EP0647030A3
公开(公告)日：1995-11-08
申请号：EP94115120.1
申请日：1994-09-26
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Mahant-Shetti, Shivaling S. , Landers, Robert J.
IPC分类号： H03K19/173 , H03K19/21
CPC分类号： H03K19/215 , H03K17/693 , H03K19/1736
摘要： A base cell device (10) includes a first transmission gate (12) configured as a multiplexer comprising an N-channel transistor (14) and a P-channel transistor (16). The base cell device (10) also includes a second transmission gate (18) configured as a multiplexer that comprises an N-channel transistor (20) and a P-channel transistor (22). The first transmission gate (12) and the second transmission gate (18) each receive a control signal C and an inverted control signal from an inverter (24). The first transmission gate (12) receives a first input signal (A) and the second transmission gate (18) receives a second input signal (B). The base cell device (10) generates a common output signal (O) from the first transmission gate (12) and the second transmission gate (18). The base cell device (10) is capable of performing all two input function operations.

10. 发明公开

EP0647030A2 Integrated circuit devices 失效
标题翻译： Integrierte Schaltungsvorrichtungen。
公开(公告)号：EP0647030A2
公开(公告)日：1995-04-05
申请号：EP94115120.1
申请日：1994-09-26
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Mahant-Shetti, Shivaling S. , Landers, Robert J.
IPC分类号： H03K19/173 , H03K19/21
CPC分类号： H03K19/215 , H03K17/693 , H03K19/1736
摘要： A base cell device (10) includes a first transmission gate (12) configured as a multiplexer comprising an N-channel transistor (14) and a P-channel transistor (16). The base cell device (10) also includes a second transmission gate (18) configured as a multiplexer that comprises an N-channel transistor (20) and a P-channel transistor (22). The first transmission gate (12) and the second transmission gate (18) each receive a control signal C and an inverted control signal from an inverter (24). The first transmission gate (12) receives a first input signal (A) and the second transmission gate (18) receives a second input signal (B). The base cell device (10) generates a common output signal (O) from the first transmission gate (12) and the second transmission gate (18). The base cell device (10) is capable of performing all two input function operations.
摘要翻译：基站装置（10）包括被配置为包括N沟道晶体管（14）和P沟道晶体管（16）的多路复用器的第一传输门（12）。基站装置（10）还包括被配置为包括N沟道晶体管（20）和P沟道晶体管（22）的多路复用器的第二传输门（18）。第一传输门（12）和第二传输门（18）各自接收来自逆变器（24）的控制信号C和反相控制信号。第一传输门（12）接收第一输入信号（A），第二传输门（18）接收第二输入信号（B）。基站装置（10）从第一传输门（12）和第二传输门（18）产生公共输出信号（O）。基站装置（10）能够执行所有两个输入功能操作。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式