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    • 2. 发明公开
    • Active overvoltage control for inductive load driving
    • AktiveÜberspannungsüberwachungfürden Betrieb einer induktiven Last。
    • EP0311576A2
    • 1989-04-12
    • EP88830401.1
    • 1988-10-04
    • SGS-THOMSON MICROELECTRONICS S.r.l.
    • Gariboldi, RobertoGola, Alberto
    • H02H9/04
    • H03K17/0826H01H47/22H02H9/047
    • A circuit for limiting the transitory's overvoltage across a power transistor connected essentially in series with an inductive load between a supply rail and a ground rail of the circuit and operated to switch ON-OFF said inductive load utilizes a comparator circuit for switching-­ON again the power transistor in order to discharge the energy stored in the load's inductance. The voltage across the power transistor is sensed by a first voltage divider, while a reference voltage is obtained by means of a second voltage divider connected between the supply and ground. The circuit is practically insensitive to temperature and to variations of the supply voltage and is easily implemented.
    • 用于限制跨越电源晶体管的短路过电压的电路,其基本上与电路的电源轨和接地轨之间的感性负载串联,并且被操作以接通 - 断开所述电感负载,利用比较器电路重新接通 功率晶体管,以便放电存储在负载电感中的能量。 功率晶体管两端的电压由第一分压器感测,而参考电压通过连接在电源和地之间的第二分压器获得。 该电路实际上对温度和电源电压的变化不敏感,并且容易实现。
    • 4. 发明公开
    • Static edgetriggered D flip-flop with a low power consumption
    • Flankengetriggertes statisches D-Flip-Flop mit geringer Leistungsaufnahme。
    • EP0567716A1
    • 1993-11-03
    • EP92830201.7
    • 1992-04-30
    • SGS-THOMSON MICROELECTRONICS S.r.l.
    • Fucili, GionaGola, Alberto
    • H03K3/356
    • H03K3/35625
    • A static, edgetriggered, D flip-flop has the second (feedback) inverter of each latch of the flip-flop structure formed by four field effect, complementary-by-pair, transistors (MP1, MN1, MP2, MN2), functionally connected in series between the supply nodes. A first pair of complementary transistors (MP2, MN2) having a source connected to one and the other supply nodes, respectively, have a gate which is connected to the supply node of opposite sign as referred to the sign of the supply node to which the respective source is connected. The other pair of complementary transistors (MP1,MN1) Have their drain connected in common to the output node (A) of the inverter, a gate connected to the output node of the first (forward) inverter (I) of the latch, and a size which is essentially smaller than the size of said first pair of complementary transistors (MP2, MN2).
    • 一个静态的edgetriggered D触发器具有由四个场效应互补的晶体管(MP1,MN1,MP2,MN2)形成的触发器结构的每个锁存器的第二(反馈)反相器,功能上连接 在供应节点之间串联。 具有连接到一个供电节点和另一供电节点的源的第一对互补晶体管(MP2,MN2)分别具有与供电节点的符号相对应的与相反符号的供电节点连接的栅极, 相应的源连接。 另一对互补晶体管(MP1,MN1)将其漏极连接到反相器的输出节点(A),栅极连接到锁存器的第一(正向)反相器(I)的输出节点,以及 其尺寸基本上小于所述第一对互补晶体管(MP2,MN2)的尺寸。