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1. 发明公开

EP0352494A1 A reduced turn-off current draw starter circuit for a stabilized band-gap voltage source in integrated circuits 失效
标题翻译：复位电路具有降低的Aufschaltstrom用于集成电路的稳定的带隙电压源。
公开(公告)号：EP0352494A1
公开(公告)日：1990-01-31
申请号：EP89111842.4
申请日：1989-06-29
申请人： SGS-THOMSON MICROELECTRONICS S.r.l.
发明人： Gola, Alberto , Pessina, Gianluigi
IPC分类号： G05F3/30
CPC分类号： G05F3/30
摘要： A starter circuit (1) for a stabilized band-gap voltage source (2), being of a type adapted to maintain a minimum electric potential value (Vba) on an output terminal (3) of said source (2) by pulling voltage from a supply pole (Vc), comprises a current mirror connected between the supply pole (Vc) and the output terminal (3) to supply that terminal with a predetermined current value (Ia). The circuit affords a greatly reduced current draw on turning off the voltage source.
摘要翻译：对于稳定的带隙电压源的起动电路（1）（2），是一种类型的angepasst对到输出端子维持最小电势值（VBA）（3）的所述源（2）通过从拉电压供给极（VC）包括连接在所述电源极（VC）和输出端子（3）以提供终端做了与预定的电流值（Ia）的之间的电流镜。该电路得到上断开电压源大大降低电流消耗。

2. 发明公开

EP0311576A2 Active overvoltage control for inductive load driving 失效
标题翻译： AktiveÜberspannungsüberwachungfürden Betrieb einer induktiven Last。
公开(公告)号：EP0311576A2
公开(公告)日：1989-04-12
申请号：EP88830401.1
申请日：1988-10-04
申请人： SGS-THOMSON MICROELECTRONICS S.r.l.
发明人： Gariboldi, Roberto , Gola, Alberto
IPC分类号： H02H9/04
CPC分类号： H03K17/0826 , H01H47/22 , H02H9/047
摘要： A circuit for limiting the transitory's overvoltage across a power transistor connected essentially in series with an inductive load between a supply rail and a ground rail of the circuit and operated to switch ON-OFF said inductive load utilizes a comparator circuit for switching-ON again the power transistor in order to discharge the energy stored in the load's inductance. The voltage across the power transistor is sensed by a first voltage divider, while a reference voltage is obtained by means of a second voltage divider connected between the supply and ground. The circuit is practically insensitive to temperature and to variations of the supply voltage and is easily implemented.
摘要翻译：用于限制跨越电源晶体管的短路过电压的电路，其基本上与电路的电源轨和接地轨之间的感性负载串联，并且被操作以接通 - 断开所述电感负载，利用比较器电路重新接通功率晶体管，以便放电存储在负载电感中的能量。功率晶体管两端的电压由第一分压器感测，而参考电压通过连接在电源和地之间的第二分压器获得。该电路实际上对温度和电源电压的变化不敏感，并且容易实现。

3. 发明公开

EP0575687A1 Power-on reset circuit having a low static consumption 失效
标题翻译： Einschalt-Rücksetzschaltungmit Niedrigem Ruhestromverbrauch。
公开(公告)号：EP0575687A1
公开(公告)日：1993-12-29
申请号：EP92830336.1
申请日：1992-06-26
申请人： SGS-THOMSON MICROELECTRONICS s.r.l.
发明人： Gola, Alberto , Fucili, Giona
IPC分类号： H03K17/22
CPC分类号： H03K17/223 , H03K2217/0036
摘要： A power-on reset circuit employs a supply voltage sensing line (M1,R1,R2,M2) for triggering a first inverter (M3,M4) of a pair of cascaded inverters (M3,M4;J). The intrinsic static consumption of such a POR circuit is strongly reduced by employing a current generator (G1,G2,R3), which is automatically forced to deliver a reduced current during the operation of the integrated circuit, for biasing two transistors functionally connected in said voltage sensing line (M1,R1,R2,M2) into a subthreshold operating condition.
摘要翻译：上电复位电路采用电源电压检测线（M1，R1，R2，M2）来触发一对级联逆变器（M3，M4; J）的第一反相器（M3，M4）。通过采用电流发生器（G1，G2，R3）大大降低了这种POR电路的固有静电消耗，电流发生器（G1，G2，R3）在集成电路的工作过程中被自动强制传递降低的电流，用于将功能上连接在所述电压感测线路（M1，R1，R2，M2）变为亚阈值运行状态。

4. 发明公开

EP0567716A1 Static edgetriggered D flip-flop with a low power consumption 失效
标题翻译： Flankengetriggertes statisches D-Flip-Flop mit geringer Leistungsaufnahme。
公开(公告)号：EP0567716A1
公开(公告)日：1993-11-03
申请号：EP92830201.7
申请日：1992-04-30
申请人： SGS-THOMSON MICROELECTRONICS S.r.l.
发明人： Fucili, Giona , Gola, Alberto
IPC分类号： H03K3/356
CPC分类号： H03K3/35625
摘要： A static, edgetriggered, D flip-flop has the second (feedback) inverter of each latch of the flip-flop structure formed by four field effect, complementary-by-pair, transistors (MP1, MN1, MP2, MN2), functionally connected in series between the supply nodes. A first pair of complementary transistors (MP2, MN2) having a source connected to one and the other supply nodes, respectively, have a gate which is connected to the supply node of opposite sign as referred to the sign of the supply node to which the respective source is connected. The other pair of complementary transistors (MP1,MN1) Have their drain connected in common to the output node (A) of the inverter, a gate connected to the output node of the first (forward) inverter (I) of the latch, and a size which is essentially smaller than the size of said first pair of complementary transistors (MP2, MN2).
摘要翻译：一个静态的edgetriggered D触发器具有由四个场效应互补的晶体管（MP1，MN1，MP2，MN2）形成的触发器结构的每个锁存器的第二（反馈）反相器，功能上连接在供应节点之间串联。具有连接到一个供电节点和另一供电节点的源的第一对互补晶体管（MP2，MN2）分别具有与供电节点的符号相对应的与相反符号的供电节点连接的栅极，相应的源连接。另一对互补晶体管（MP1，MN1）将其漏极连接到反相器的输出节点（A），栅极连接到锁存器的第一（正向）反相器（I）的输出节点，以及其尺寸基本上小于所述第一对互补晶体管（MP2，MN2）的尺寸。

5. 发明公开

EP0760558A1 D flip-flop having asynchronous data loading 失效
标题翻译： D-Flip-Flop mit asynchronem Laden von Daten
公开(公告)号：EP0760558A1
公开(公告)日：1997-03-05
申请号：EP95830370.3
申请日：1995-08-31
申请人： SGS-THOMSON MICROELECTRONICS S.r.l.
发明人： Fucili, Giona , Papillo, Lorenzo , Pasquino, Andrea , Rossi, Annamaria , Gola, Alberto
IPC分类号： H03K3/037 , H03K3/3562
CPC分类号： H03K3/0372 , H03K3/35625
摘要： A flip-flop of the D type capable of loading data asynchronously and comprising two latches, a master and a slave one, connected in series with each other, is characterized in that each of these comprises an interface and selection circuit (MUX1,MUX2) for input signals transferable in either the synchronous or the asynchronous manner, and a logic gate circuit (ND1,ND2) which is input such signals and, in an asynchronous manner, control signals effective to establish the latch own states.
摘要翻译：能够异步加载数据并且包括彼此串联连接的两个锁存器（主机和从机）的D型触发器的特征在于，它们中的每一个包括接口和选择电路（MUX1，MUX2）对于以同步或异步方式传输的输入信号，以及输入这种信号的逻辑门电路（ND1，ND2），并且以异步方式，有效地建立锁存器自身状态的控制信号。

6. 发明授权

EP0575687B1 Power-on reset circuit having a low static consumption 失效
标题翻译：上电复位电路，低静态电流消耗
公开(公告)号：EP0575687B1
公开(公告)日：1997-01-29
申请号：EP92830336.1
申请日：1992-06-26
申请人： SGS-THOMSON MICROELECTRONICS s.r.l.
发明人： Gola, Alberto , Fucili, Giona
IPC分类号： H03K17/22
CPC分类号： H03K17/223 , H03K2217/0036

7. 发明授权

EP0321795B1 Pilot circuit with integrated circuit with preset firing delay for MOS power transistors 失效
标题翻译：与为MOS功率晶体管预设点火延迟集成电路的控制电路。
公开(公告)号：EP0321795B1
公开(公告)日：1995-04-26
申请号：EP88120537.1
申请日：1988-12-08
申请人： SGS-THOMSON MICROELECTRONICS s.r.l.
发明人： Gola, Alberto , Pessina, Gianluigi
IPC分类号： H03K17/30 , H03K17/16 , H03K17/725
CPC分类号： G11B19/20 , H03K17/04123 , H03K17/04206 , H03K17/145 , H03K17/284

8. 发明公开

EP0321795A3 Pilot circuit with integrated circuit with preset firing delay for MOS power transistors 失效
标题翻译：具有用于MOS功率晶体管的预置快速延迟的集成电路的引导电路
公开(公告)号：EP0321795A3
公开(公告)日：1991-01-23
申请号：EP88120537.1
申请日：1988-12-08
申请人： SGS-THOMSON MICROELECTRONICS S.r.l.
发明人： Gola, Alberto , Pessina, Gianluigi
IPC分类号： H03K17/30 , H03K17/16 , H03K17/725
CPC分类号： G11B19/20 , H03K17/04123 , H03K17/04206 , H03K17/145 , H03K17/284
摘要： The pilot circuit comprises an R-C network consisting of a condenser (Cx) inserted between a gate terminal of the MOS transistor (M) and ground and a resistance (Rx) for charging said condenser (Cx). In parallel with the resistance (Rx) there is placed an SCR circuit (Q1, Q2, Q3) with associated threshhold circuit (Q3, R1, R2, R3) which permits firing of the SCR circuit (Q1, Q2, Q3) when the charge voltage of the condenser (Cx) reaches a preset threshhold.

9. 发明授权

EP0429829B1 An electronic comparator circuit 失效
标题翻译：电子比较器电路
公开(公告)号：EP0429829B1
公开(公告)日：1997-04-09
申请号：EP90119872.1
申请日：1990-10-17
申请人： SGS-THOMSON MICROELECTRONICS S.r.l.
发明人： Gola, Alberto , Alzati, Angelo , Novelli, Aldo
IPC分类号： H03K5/24 , H03F3/45
CPC分类号： H03F3/4508 , H03F3/45076 , H03F3/45179 , H03F3/45286 , H03F3/45291 , H03F2203/45028 , H03F2203/45144 , H03F2203/45188 , H03F2203/45304 , H03F2203/45612 , H03K5/2445

10. 发明授权

EP0311576B1 Active overvoltage control for inductive load driving 失效
标题翻译：有源过电压监视电感性负载的操作。
公开(公告)号：EP0311576B1
公开(公告)日：1994-02-23
申请号：EP88830401.1
申请日：1988-10-04
申请人： SGS-THOMSON MICROELECTRONICS s.r.l.
发明人： Gariboldi, Roberto , Gola, Alberto
IPC分类号： H02H9/04
CPC分类号： H03K17/0826 , H01H47/22 , H02H9/047

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