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1. 发明公开

EP0556744A1 Device for limiting the working voltage for mechanical switches in telephony 失效
标题翻译： Vorrichtung zum Begrenzen der Arbeitsspannungfürmechanische Schalter im Fernsprechwesen。
公开(公告)号：EP0556744A1
公开(公告)日：1993-08-25
申请号：EP93102240.4
申请日：1993-02-12
申请人： SGS-THOMSON MICROELECTRONICS S.r.l.
发明人： Andreini, Antonio , Consiglio, Pietro , Erratico, Pietro , Ravanelli, Enrico Maria Alfonso
IPC分类号： H04M1/74 , H04M1/08
CPC分类号： H04M1/74 , H04M1/312 , H04M1/82
摘要： Device for limiting the working voltage for mechanical switches in telephony includes terminals (20,21) for connection to a telephone line, a connection and power supply branch for a control circuit (24) extending from a first terminal (21), the branch having a first switch (25), the cathode terminal of a first Zener diode (26) and the source terminal of a first MOSFET transistor (27) being connected to the output terminal of the first switch (25), the gate terminal of the first MOSFET transistor (27) being connected, through the anode terminal of the Zener diode (26), to the first terminal. The current absorbed by the device may be adjusted.
摘要翻译：用于限制电话机械开关的工作电压的装置包括用于连接到电话线的端子（20,21），用于从第一端子（21）延伸的控制电路（24）的连接和电源分支，所述分支具有第一开关（25），第一齐纳二极管（26）的阴极端子和第一MOSFET晶体管（27）的源极端子连接到第一开关（25）的输出端子，第一开关 MOSFET晶体管（27）通过齐纳二极管（26）的阳极端子连接到第一端子。可以调节装置吸收的电流。

2. 发明公开

EP0844661A1 A process for the production of silicon gate CMOS transistors, and resultant product 失效
标题翻译： Silicium Gate CMOS-Transistore und Verfahren zu ihrer Herstellung
公开(公告)号：EP0844661A1
公开(公告)日：1998-05-27
申请号：EP96830590.4
申请日：1996-11-20
申请人： SGS-THOMSON MICROELECTRONICS s.r.l.
发明人： Depetro, Riccardo , Andreini, Antonio
IPC分类号： H01L21/8238
CPC分类号： H01L21/823814
摘要： A process is described for the production of silicon gate CMOS transistors in which, after formation of strips (14n, 14p) of polycrystalline silicon for the gate electrodes on the active areas intended for the n-channel and p-channel transistors, an implantation mask (15) is formed which leaves exposed the active areas for the n-channel transistors and the associated strips (14n) of polycrystalline silicon up to the zones (14z) where these are intended to be contacted by respective metal electrodes, in such a way as to dope with n-type impurities not only the source and drain regions but also the polycrystalline silicon strips (14n). A similar operation allows both the source and drain regions of the p-channel transistors and the associated strips (14p) of polycrystalline silicon for the gate electrodes up to the respective contact zones for the metal electrodes to be doped with p-type impurities. In this way p-channel transistors having lower threshold voltages than those obtainable with the usual processes are obtained without additional operations.
摘要翻译：描述了用于生产硅栅极CMOS晶体管的工艺，其中在用于n沟道和p沟道晶体管的有源区上形成用于栅电极的多晶硅的条（14n，14p），注入掩模（15）形成，其暴露了用于n沟道晶体管的有源区域和相关联的多晶硅条（14n）直到这些将被各个金属电极接触的区域（14z），以这种方式为了掺杂n型杂质不仅源区和漏区，而且多晶硅条（14n）。类似的操作允许p沟道晶体管的源极和漏极区域以及用于栅电极的相关联的多晶硅条（14p）直到金属电极的相应接触区域掺杂有p型杂质。以这种方式，获得具有比通常处理可获得的阈值电压低的阈值电压的p沟道晶体管，而无需额外的操作。

3. 发明公开

EP0741416A1 Thin epitaxy RESURF ic containing HV p-ch and n-ch devices with source or drain not tied to grounds potential 失效
标题翻译：与用于高电压的P沟道和N沟道器件的薄外延层RESURF IC，其中源极和漏极不连接到地电位
公开(公告)号：EP0741416A1
公开(公告)日：1996-11-06
申请号：EP95830176.4
申请日：1995-05-02
申请人： SGS-THOMSON MICROELECTRONICS S.r.l.
发明人： Depetro, Riccardo , Contiero, Claudio , Andreini, Antonio
IPC分类号： H01L29/00 , H01L27/092 , H01L27/06
CPC分类号： H01L29/0878 , H01L27/0623 , H01L27/0922 , H01L29/0615 , H01L29/0619 , H01L29/1083 , H01L29/42368 , H01L29/7816 , H01L29/7835
摘要： N-channel LDMOS and p-channel MOS devices for high voltage integrated in a BiCMOS integrated circuit and exploiting a RESURF condition are provided with a buried region of the same type of conductivity of the epitaxial layer and a doping level intermediate between the doping level of the epitaxial layer and of a source or drain region, respectively, of the high voltage complementary MOS devices. The devices may be configured as source or drain followers without problems.
摘要翻译：用于高电压集成在的BiCMOS集成电路和利用一个RESURF条件的N沟道LDMOS和p沟道MOS器件设有的掺杂电平之间的中间的相同类型的外延层的导电性和掺杂水平的的掩埋区在外延层和源极的区或漏区，分别为高电压互补MOS器件。该装置可被配置为源极或漏极的追随者没有问题。

4. 发明公开

EP0239060A2 Method for manufacturing semiconductor integrated circuits including cmos and high-voltage electronic devices 失效
标题翻译：一种用于CMOS的制造和高电压电子部件内置半导体器件的过程。
公开(公告)号：EP0239060A2
公开(公告)日：1987-09-30
申请号：EP87104271.9
申请日：1987-03-24
申请人： SGS-THOMSON MICROELECTRONICS S.r.l.
发明人： Andreini, Antonio , Contiero, Claudio , Galbiati, Paola
IPC分类号： H01L21/76 , H01L21/82 , H01L27/06
CPC分类号： H01L21/8236 , H01L21/033 , H01L21/823456 , H01L27/0922
摘要： This method, requiring a reduced number of process phases and providing an efficient, high-voltage structure, comprises forming a P-well region of the N-channel transistor of a CMOS device, by means of boron atom implant through a protective mask, forming at least one insulation region surrounding the CMOS device, forming edge regions having the same conductivity type as the insulation region but with a smaller concentration of impurities on at least one part of the insulation region and in the high-voltage electronic devices by means of the same boron atom implant used to form the P-well region.
摘要翻译：该方法中，需要工艺阶段的数量减少，高效，高电压结构的提供，包括通过保护掩膜形成CMOS器件的N沟道晶体管的P阱区域，通过硼原子植入物来实现，从而形成至少一个绝缘区域包围所述CMOS装置中，通过的方式形成具有相同导电类型的绝缘区域，但与在该绝缘区域的至少一个部分和在高电压电子设备杂质的浓度较小的边缘区域相同硼原子注入用于形成P阱区。

5. 发明授权

EP0231811B1 Method for manufacturing integrated electronic devices, in particular high voltage P-channel MOS transistors 失效
标题翻译：用于生产的集成电子器件，特别是高电压的P沟道MOS晶体管的方法。
公开(公告)号：EP0231811B1
公开(公告)日：1993-12-15
申请号：EP87100765.4
申请日：1987-01-21
申请人： SGS-THOMSON MICROELECTRONICS s.r.l.
发明人： Contiero, Claudio , Galbiati, Paola , Andreini, Antonio
IPC分类号： H01L21/82 , H01L21/265
CPC分类号： H01L21/8249 , H01L21/22 , H01L21/2253 , H01L21/2652 , H01L21/8234 , H01L21/8236 , H01L21/8238

6. 发明授权

EP0244366B1 Self-aligned process for fabricating small size DMOS cells and MOS devices obtained by means of said process 失效
标题翻译：用于制造小尺寸DMOS细胞的自对准方法和通过实例方法获得的MOS器件
公开(公告)号：EP0244366B1
公开(公告)日：1992-05-13
申请号：EP87830063.1
申请日：1987-02-23
申请人： SGS-THOMSON MICROELECTRONICS s.r.l.
发明人： Contiero, Claudio , Andreini, Antonio , Galbiati, Paola
IPC分类号： H01L29/78
CPC分类号： H01L29/66719 , H01L21/0337 , H01L29/1095 , H01L29/66712

7. 发明公开

EP0231811A2 Method for manufacturing integrated electronic devices, in particular high voltage P-channel MOS transistors 失效
标题翻译：用于生产的集成电子器件，特别是高电压的P沟道MOS晶体管的方法。
公开(公告)号：EP0231811A2
公开(公告)日：1987-08-12
申请号：EP87100765.4
申请日：1987-01-21
申请人： SGS-THOMSON MICROELECTRONICS S.r.l.
发明人： Contiero, Claudio , Galbiati, Paola , Andreini, Antonio
IPC分类号： H01L21/82 , H01L21/265
CPC分类号： H01L21/8249 , H01L21/22 , H01L21/2253 , H01L21/2652 , H01L21/8234 , H01L21/8236 , H01L21/8238
摘要： This method, requiring a smaller number of masking steps with respect to the known methods, comprises boron implant (25) on the surface of an epitaxial layer (2), without masking, and arsenic implant (28) in predetermined locations of the epitaxial layer surface by means of an appropriate mask (27). A subsequent thermal treatment then leads to diffusion of the implanted arsenic and boron atoms (72,35-37), but boron diffusion in the regions in which arsenic implant has also occurred is prevented by the interaction with the latter, to thereby obtain regions with an N⁺ type conductivity where both boron and arsenic have been implanted and regions of P type conductivity where only boron has been implanted

8. 发明授权

EP0239060B1 Method for manufacturing semiconductor integrated circuits including cmos and high-voltage electronic devices 失效
标题翻译：一种用于CMOS的制造和高电压电子部件内置半导体器件的过程。
公开(公告)号：EP0239060B1
公开(公告)日：1995-05-24
申请号：EP87104271.9
申请日：1987-03-24
申请人： SGS-THOMSON MICROELECTRONICS s.r.l.
发明人： Andreini, Antonio , Contiero, Claudio , Galbiati, Paola
IPC分类号： H01L21/76 , H01L21/82 , H01L27/06
CPC分类号： H01L21/8236 , H01L21/033 , H01L21/823456 , H01L27/0922

9. 发明公开

EP0239060A3 Method for manufacturing semiconductor integrated circuits including cmos and high-voltage electronic devices 失效
标题翻译：制造半导体集成电路的方法，包括CMOS和高压电子器件
公开(公告)号：EP0239060A3
公开(公告)日：1989-11-15
申请号：EP87104271.9
申请日：1987-03-24
申请人： SGS-THOMSON MICROELECTRONICS S.r.l.
发明人： Andreini, Antonio , Contiero, Claudio , Galbiati, Paola
IPC分类号： H01L21/76 , H01L21/82 , H01L27/06
CPC分类号： H01L21/8236 , H01L21/033 , H01L21/823456 , H01L27/0922
摘要： This method, requiring a reduced number of process phases and providing an efficient, high-voltage structure, comprises forming a P-well region of the N-channel transistor of a CMOS device, by means of boron atom implant through a protective mask, forming at least one insulation region surrounding the CMOS device, forming edge regions having the same conductivity type as the insulation region but with a smaller concentration of impurities on at least one part of the insulation region and in the high-voltage electronic devices by means of the same boron atom implant used to form the P-well region.

10. 发明公开

EP0244366A2 Self-aligned process for fabricating small size DMOS cells and MOS devices obtained by means of said process 失效
标题翻译：用于生产小DMOS单元和自对准工艺通过该方法MOS器件获得。
公开(公告)号：EP0244366A2
公开(公告)日：1987-11-04
申请号：EP87830063.1
申请日：1987-02-23
申请人： SGS-THOMSON MICROELECTRONICS S.r.l.
发明人： Contiero, Claudio , Andreini, Antonio , Galbiati, Paola
IPC分类号： H01L29/78
CPC分类号： H01L29/66719 , H01L21/0337 , H01L29/1095 , H01L29/66712
摘要： Described is an improved fabrication process for vertical DMOS cells contemplating the prior definition of the gate areas by placing a polycrystalline silicon gate electrode and utilizing the gate electrode itself as a mask for implanting and diffusing the body regions, while forming the short region is carried out using self-alignment techniques which permit an easy control of the lateral extention of the region itself. A noncritical mask defines the zone where the short circuiting contact between the source electrode and the source and body regions in the middle of the DMOS cell will be made, allowing also to form the source region. Opening of the relative contact is also effected by self alignment technique, further simplifying the process.
摘要翻译：描述的是用于垂直DMOS细胞通过将多晶硅栅电极和利用所述栅电极本身作为用于植入和扩散体区域的掩模考虑栅极区域的现有定义，而形成短区域中进行的改进的制造工艺使用自对准技术，其允许该区域本身的横向extention的容易的控制。阿非关键掩模定义，其中在DMOS单元的中间的源电极和源极区和本体区之间的短路接触将要进行的区域，因此允许以形成源极区域。相对接触的开口，以便通过自对准技术来实现，从而进一步简化该过程。

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