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1. 发明授权

EP0390452B1 Synchronization circuit using N-bit counters in a memory circuit 失效
标题翻译：用N位计数器同步电路在存储装置中操作
公开(公告)号：EP0390452B1
公开(公告)日：1997-03-05
申请号：EP90303170.6
申请日：1990-03-23
申请人： SGS-THOMSON MICROELECTRONICS, INC.
发明人： McClure, David Charles , Lysinger, Mark Alan
IPC分类号： H03K3/037 , H03K23/50 , H04J3/06
CPC分类号： H04J3/0626

2. 发明公开

EP0437081A3 Redundancy for serial memory 失效
标题翻译：冗余用于串行存储器
公开(公告)号：EP0437081A3
公开(公告)日：1992-07-15
申请号：EP90314116.6
申请日：1990-12-21
申请人： SGS-THOMSON MICROELECTRONICS, INC.
发明人： McClure, David Charles , Lysinger, Mark Alan
IPC分类号： G06F11/20
CPC分类号： G11C29/86 , G11C8/04
摘要： A fault tolerant sequential memory includes primary and redundant memory rows (or columns) and primary and redundant shift registers. The redundant memory rows (or columns) and redundant shift registers are formed at the end of the serial chain. Each shift register of each primary and redundant memory block is interconnected with an independent, separately programmable multiplexer logic circuit. Each multiplexer logic circuit includes an independently programmable repair buffer for logically bypassing a defective primary memory block and associated shift registers within the primary memory array. Each redundant memory block includes a multiplexer logic circuit having an independently programmable repair buffer for logically enabling a redundant memory block and shift register at the end of the serial chain. Consequently, a faulty memory block, including its shift register and memory row (or column) is bypassed and is effectively removed from the shifting sequence. The redundant memory block, including a redundant shift register and a redundant row (or column), is inserted at the end of the shift register chain by opening a programmable fuse element.

3. 发明公开

EP0547891A3 A precharging output driver circuit 失效
标题翻译：预置输出驱动电路
公开(公告)号：EP0547891A3
公开(公告)日：1993-12-08
申请号：EP92311513.3
申请日：1992-12-16
申请人： SGS-THOMSON MICROELECTRONICS, INC.
发明人： McClure, David Charles , Lysinger, Mark Alan , Slemmer, William Carl
IPC分类号： H03K19/0175 , H03K19/003 , G11C7/00
CPC分类号： H03K19/00361
摘要： A push-pull output driver circuit is disclosed which includes control circuitry for controlling the gates of the driver transistors to effect precharge of the output terminal at the beginning of a cycle. Precharge is initiated at the beginning of each cycle, for example indicated by an address transition. The prior data state at the output is stored, and enables the opposing driver transistor from that which drove the stored prior data state by enabling a gated level detector with hysteresis, such as a Schmitt trigger, associated therewith. The transistor that drove the stored prior data state is disabled, thus precluding oscillations during precharge. The gated Schmitt triggers each receive the voltage of the output terminal and, when enabled, turn on a transistor which couples the output terminal to the gate of the driver transistor. The Schmitt triggers also control the precharge to terminate when the output terminal has reached an intermediate voltage, and so that oscillations are minimized as a result of the hysteresis characteristic. Connection of the output terminal to the gate of the precharging driver transistor helps to eliminate overshoot during precharge.

4. 发明公开

EP0437081A2 Redundancy for serial memory 失效
标题翻译： Redundanzfürserielle Speicher。
公开(公告)号：EP0437081A2
公开(公告)日：1991-07-17
申请号：EP90314116.6
申请日：1990-12-21
申请人： SGS-THOMSON MICROELECTRONICS, INC.
发明人： McClure, David Charles , Lysinger, Mark Alan
IPC分类号： G06F11/20
CPC分类号： G11C29/86 , G11C8/04
摘要： A fault tolerant sequential memory includes primary and redundant memory rows (or columns) and primary and redundant shift registers. The redundant memory rows (or columns) and redundant shift registers are formed at the end of the serial chain. Each shift register of each primary and redundant memory block is interconnected with an independent, separately programmable multiplexer logic circuit. Each multiplexer logic circuit includes an independently programmable repair buffer for logically bypassing a defective primary memory block and associated shift registers within the primary memory array. Each redundant memory block includes a multiplexer logic circuit having an independently programmable repair buffer for logically enabling a redundant memory block and shift register at the end of the serial chain. Consequently, a faulty memory block, including its shift register and memory row (or column) is bypassed and is effectively removed from the shifting sequence. The redundant memory block, including a redundant shift register and a redundant row (or column), is inserted at the end of the shift register chain by opening a programmable fuse element.
摘要翻译：容错顺序存储器包括主和冗余存储器行（或列）以及主冗余移位寄存器。冗余存储器行（或列）和冗余移位寄存器形成在串行链的末尾。每个主和冗余存储器块的每个移位寄存器与独立的，单独可编程的多路复用器逻辑电路互连。每个多路复用器逻辑电路包括独立可编程的修复缓冲器，用于逻辑地绕过主存储器阵列中的有缺陷的主存储器块和相关联的移位寄存器。每个冗余存储器块包括具有独立可编程修复缓冲器的多路复用器逻辑电路，用于逻辑地使能串行链末端的冗余存储器块和移位寄存器。因此，包括其移位寄存器和存储器行（或列）的故障存储器块被旁路并且被有效地从移位序列中移除。包括冗余移位寄存器和冗余行（或列）的冗余存储块通过打开可编程保险丝元件插入移位寄存器链的末端。

5. 发明公开

EP0745859A2 Configurable probe pads to facilitate parallel testing of integrated circuit devices 失效
标题翻译： Konfigurierbare Kontaktleiste zur bequemen parallellenPrüfungvon integrierten Schaltungen
公开(公告)号：EP0745859A2
公开(公告)日：1996-12-04
申请号：EP96302949.1
申请日：1996-04-26
申请人： SGS-THOMSON MICROELECTRONICS, INC.
发明人： Brannigan, Michael Joseph , Lysinger, Mark Alan , McClure, David Charles
IPC分类号： G01R1/04
CPC分类号： G01R31/2884 , G01R31/2831 , G11C29/48
摘要： According to the present invention, parallel testing of integrated circuit devices are facilitated such that it is not necessary that integrated circuit devices to be parallel tested be "ends only" devices. A side pad located along the sides, rather than the ends, of the integrated circuit device is electrically connected by muitiplexing circuitry to a corresponding configurable probe pad located along the ends of the device. During parallel testing of the device, the side pad is effectively tested when the configurable probe pad is probed and tested. While the configurable probe pad is tested during parallel testing, the side pad is not directly exercised. Following parallel testing, the side pad is bonded to the device package but the configurable probe pad is not bonded to the device package.
摘要翻译：根据本发明，集成电路器件的并行测试方便，因此并不需要将并联测试的集成电路器件设为“仅限端”器件。沿着集成电路器件的侧面而不是端部设置的侧焊盘通过多路复用电路电连接到沿着器件的端部设置的对应的可配置探针焊盘。在对器件进行并行测试时，可以对可配置的探头焊盘进行探测和测试时，对侧面焊盘进行有效测试。虽然在并行测试期间对可配置的探头焊盘进行了测试，但是侧面垫没有直接运行。在进行并行测试之后，侧面焊盘接合到器件封装，但是可配置的探针焊盘没有粘合到器件封装。

6. 发明公开

EP0547891A2 A precharging output driver circuit 失效
标题翻译： Ausgangstreiberschaltung mit Vorladung。
公开(公告)号：EP0547891A2
公开(公告)日：1993-06-23
申请号：EP92311513.3
申请日：1992-12-16
申请人： SGS-THOMSON MICROELECTRONICS, INC.
发明人： McClure, David Charles , Lysinger, Mark Alan , Slemmer, William Carl
IPC分类号： H03K19/0175 , H03K19/003 , G11C7/00
CPC分类号： H03K19/00361
摘要： A push-pull output driver circuit is disclosed which includes control circuitry for controlling the gates of the driver transistors to effect precharge of the output terminal at the beginning of a cycle. Precharge is initiated at the beginning of each cycle, for example indicated by an address transition. The prior data state at the output is stored, and enables the opposing driver transistor from that which drove the stored prior data state by enabling a gated level detector with hysteresis, such as a Schmitt trigger, associated therewith. The transistor that drove the stored prior data state is disabled, thus precluding oscillations during precharge. The gated Schmitt triggers each receive the voltage of the output terminal and, when enabled, turn on a transistor which couples the output terminal to the gate of the driver transistor. The Schmitt triggers also control the precharge to terminate when the output terminal has reached an intermediate voltage, and so that oscillations are minimized as a result of the hysteresis characteristic. Connection of the output terminal to the gate of the precharging driver transistor helps to eliminate overshoot during precharge.
摘要翻译：公开了一种推挽输出驱动器电路，其包括控制电路，用于控制驱动晶体管的栅极以在一个周期开始时实现输出端子的预充电。预充电在每个周期开始时启动，例如由地址转换指示。存储输出端的先前数据状态，并通过启用与其相关联的具有滞后的门控电平检测器（例如施密特触发器）使相对的驱动器晶体管能够驱动存储的先前数据状态。驱动存储的先前数据状态的晶体管被禁用，从而阻止在预充电期间的振荡。门控施密特触发器每个都接收输出端子的电压，并且在使能时，打开将输出端子耦合到驱动晶体管的栅极的晶体管。当输出端子达到中间电压时，施密特触发器也可控制预充电，从而由于滞后特性使振荡最小化。将输出端子连接到预充电驱动晶体管的栅极有助于在预充电期间消除过冲。

7. 发明公开

EP0837562A3 A precharging output driver circuit 失效
标题翻译：预充电输出驱动器电路
公开(公告)号：EP0837562A3
公开(公告)日：1998-05-20
申请号：EP98100115.9
申请日：1992-12-16
申请人： SGS-THOMSON MICROELECTRONICS, INC.
发明人： McClure, David Charles , Lysinger, Mark Alan , Slemmer, William Carl
IPC分类号： H03K19/003 , H03K19/017 , G11C7/00
CPC分类号： H03K19/00361
摘要： A push-pull output driver circuit is disclosed which includes control circuitry for controlling the gates of the driver transistors to effect precharge of the output terminal at the beginning of a cycle. Precharge is initiated at the beginning of each cycle, for example indicated by an address transition. The prior data state at the output is stored, and enables the opposing driver transistor from that which drove the stored prior data state by enabling a gated level detector with hysteresis, such as a Schmitt trigger, associated therewith. The transistor that drove the stored prior data state is disabled, thus precluding oscillations during precharge. The gated Schmitt triggers each receive the voltage of the output terminal and, when enabled, turn on a transistor which couples the output terminal to the gate of the driver transistor. The Schmitt triggers also control the precharge to terminate when the output terminal has reached an intermediate voltage, and so that oscillations are minimized as a result of the hysteresis characteristic. Connection of the output terminal to the gate of the precharging driver transistor helps to eliminate overshoot during precharge.
摘要翻译：公开了一种推挽输出驱动器电路，其包括控制电路，用于控制驱动器晶体管的栅极以在周期开始时对输出端子进行预充电。预充电在每个周期开始时启动，例如由地址转换指示。存储输出端处的先前数据状态，并且通过启用具有滞后的门控电平检测器（例如与之相关联的施密特触发器）来启用与驱动所存储的在先数据状态的驱动晶体管相反的驱动晶体管。驱动所存储的先前数据状态的晶体管被禁用，因此排除了预充电期间的振荡。门控施密特触发每个接收输出端子的电压，并且当被使能时，导通将输出端子耦合到驱动晶体管的栅极的晶体管。施密特触发器还控制预充电，当输出端子达到中间电压时终止，并且由于滞后特性而使振荡最小化。输出端连接到预充电驱动晶体管的栅极有助于消除预充电期间的过冲。

8. 发明公开

EP0745859A3 Configurable probe pads to facilitate parallel testing of integrated circuit devices 失效
标题翻译：用于集成电路的容易平行测试配置的接触带
公开(公告)号：EP0745859A3
公开(公告)日：1997-08-06
申请号：EP96302949.1
申请日：1996-04-26
申请人： SGS-THOMSON MICROELECTRONICS, INC.
发明人： Brannigan, Michael Joseph , Lysinger, Mark Alan , McClure, David Charles
IPC分类号： G01R1/04
CPC分类号： G01R31/2884 , G01R31/2831 , G11C29/48
摘要： According to the present invention, parallel testing of integrated circuit devices are facilitated such that it is not necessary that integrated circuit devices to be parallel tested be "ends only" devices. A side pad located along the sides, rather than the ends, of the integrated circuit device is electrically connected by muitiplexing circuitry to a corresponding configurable probe pad located along the ends of the device. During parallel testing of the device, the side pad is effectively tested when the configurable probe pad is probed and tested. While the configurable probe pad is tested during parallel testing, the side pad is not directly exercised. Following parallel testing, the side pad is bonded to the device package but the configurable probe pad is not bonded to the device package.

9. 发明授权

EP0437081B1 Redundancy for serial memory 失效
标题翻译：冗余串行存储器
公开(公告)号：EP0437081B1
公开(公告)日：1997-04-23
申请号：EP90314116.6
申请日：1990-12-21
申请人： SGS-THOMSON MICROELECTRONICS, INC.
发明人： McClure, David Charles , Lysinger, Mark Alan
IPC分类号： G06F11/20
CPC分类号： G11C29/86 , G11C8/04

10. 发明公开

EP0390453A2 Circuitry and method for providing an output signal indicative of the time delay between two asynchronous clock signals 失效
标题翻译：电路和方法，用于为两个异步时钟之间的时间延迟的代表性的恢复信号的输出信号。
公开(公告)号：EP0390453A2
公开(公告)日：1990-10-03
申请号：EP90303171.4
申请日：1990-03-23
申请人： SGS-THOMSON MICROELECTRONICS, INC.
发明人： McClure, David Charles , Lysinger, Mark Alan
IPC分类号： G06F5/06 , G01R29/02
CPC分类号： G06F5/12 , G01R29/0273 , G06F7/026 , G06F2205/126
摘要： In the preferred embodiment of the invention, a first-in, first-out (FIFO) memory includes flag generation circuitry which utilizes a write clock counter and a read clock counter to provide the number of write clock pulses received. since the previous write reset signal and the number of read clock pulses received by the FIFO since the previous read reset signal. A subtractor circuit subtracts the number of read clock pulses from the number of write clock pulses, and this difference is compared in a comparator circuit to determine if the difference is greater than a preset value. This determination provides the information as to the relative fullness of the FIFO.
摘要翻译：在本发明的优选实施方式，以先入，先出（FIFO）存储器包括标志生成电路，其利用写时钟计数器和读时钟计数器，以提供接收到的写时钟脉冲的数目。由于先前的写复位信号和从先前读出的复位信号由FIFO接收的读出时钟脉冲数。减法器电路中减去从写入时钟脉冲数读出时钟脉冲的数量，并且该差值与一个比较器电路，以确定性矿如果该差大于预先设定的值大。这种判断提供信息到FIFO的相对丰满。

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