会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 4. 发明公开
    • CURRENT SWITCH CELL AND DIGITAL/ANALOG CONVERTER
    • Stromschalterzelle和Digital-Analog-Wandler
    • EP2383894A1
    • 2011-11-02
    • EP10735875.6
    • 2010-01-28
    • Nippon Telegraph And Telephone Corporation
    • NAGATANI, MunehikoNOSAKA, HideyukiYAMANAKA, ShogoSANO, KimikazuMURATA, Koichi
    • H03M1/74
    • H03M1/662H03M1/742
    • Two D flip-flops (D-FF MA , D-FF MB ) output two half-rate signals (D MR-A , D MR-B ) by dividing a digital input signal (D M ) into two signals and retiming them based on a clock signal (CLK) and a negative-phase clock signal (CLKB). First and second switches (S M1 , S M2 ) are driven by the two half-rate signals (D MR-A , D MR-B ). Third and fourth switches (S M3 , S M4 ) are driven by a select signal SW and a negative-phase select signal SWB that have the same frequency as that of the clock signal (CLK) but a different phase from that of the clock signal (CLK). The current supplied from a current source (1) to a load (4) thus becomes a current signal corresponding to a conversion frequency twice the frequency of the clock signal (CLK).
    • 两个D触发器(D-FFMA,D-FF MB)通过将数字输入信号(DM)分成两个信号并基于它们重新定时输出两个半速率信号(D MR-A,D MR-B) 时钟信号(CLK)和负相位时钟信号(CLKB)。 第一和第二开关(S M1,S M2)由两个半速率信号(D MR-A,D MR-B)驱动。 第三和第四开关(S M3,S M4)由与时钟信号(CLK)的频率相同的频率的选择信号SW和负相位选择信号SWB驱动,但与时钟信号的相位不同 (CLK)。 因此,从电流源(1)提供给负载(4)的电流变为对应于时钟信号(CLK)频率的两倍的转换频率的电流信号。