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1. 发明授权

EP2195922B1 AUTOMATIC COMMON-MODE REJECTION CALIBRATION 有权
标题翻译：自动共模抑制校准
公开(公告)号：EP2195922B1
公开(公告)日：2015-03-04
申请号：EP08807654.2
申请日：2008-09-15
申请人： NXP B.V.
发明人： SEBASTIANO, Fabio , BREEMS, Lucien, Johannes , ROOVERS, Raf, Lodewijk, Jan
IPC分类号： H03F1/30 , H03F3/45
CPC分类号： H03F1/304 , H03F3/4565 , H03F2203/45448 , H03F2203/45456 , H03F2203/45471 , H03F2203/45504

2. 发明授权

EP1961115B1 CIRCUIT ELECTRONIQUE A COMPENSATION DE DECALAGE INTRINSEQUE DE PAIRES DIFFERENTIELLES 有权
标题翻译：利用差分对的补偿内在OFFSETS电子电路
公开(公告)号：EP1961115B1
公开(公告)日：2009-04-08
申请号：EP06830542.4
申请日：2006-12-12
申请人： E2V Semiconductors
发明人： BORE, François , BRUEL, Sandrine
IPC分类号： H03F3/45 , H03M3/00
CPC分类号： H03F3/45748 , H03F3/456 , H03F2203/45212 , H03F2203/45352 , H03F2203/45482 , H03F2203/45504 , H03F2203/45512 , H03F2203/45514 , H03M1/445
摘要： The invention relates to analogue integrated electronic circuits using differential pairs (T1, T2). An automatic method of correcting offset voltage is proposed, comprising the following steps: short-circuiting the inputs (V1, V2) of the differential circuit during a calibration phase that is distinct from the normal usage phase; charging a capacitance through the difference in the output currents of the branches of the differential pair in this phase; comparing the voltage across the terminals of the capacitance with at least one threshold; retaining in memory, during the normal usage phase following the calibration phase, the result of the comparison; applying, in the normal usage phase, a correction dependent on the result retained in memory to a current source (SC1, SC2) of a follower stage upstream of the differential pair.

3. 发明授权

EP1418669B1 Semiconductor integrated circuit device and wireless communication system 有权
标题翻译：的半导体集成电路和无线通信系统
公开(公告)号：EP1418669B1
公开(公告)日：2007-12-05
申请号：EP03023256.5
申请日：2003-10-14
申请人： Renesas Technology Corp.
发明人： Irie, Kiyoshi, Renesas Technology Corp. , Hori, Kazuaki, Renesas Technology Corp. , Hikasa, Kazuhiko, Renesas Technology Corp.
IPC分类号： H03G3/30
CPC分类号： H03G1/0088 , H03F3/45098 , H03F2200/294 , H03F2203/45496 , H03F2203/45504 , H03F2203/45722 , H03G1/0023 , H04B1/707 , H04B2201/70706

4. 发明公开

EP0718741A3 Voltage regulator for an output driver with reduced output impedance 失效
标题翻译：用于降低输出阻抗的输出驱动器的电压调节器
公开(公告)号：EP0718741A3
公开(公告)日：1996-07-03
申请号：EP95309306.9
申请日：1995-12-20
申请人： SGS-THOMSON MICROELECTRONICS, INC.
发明人： McClure, David C.
IPC分类号： G05F1/46
CPC分类号： H03F3/45479 , G05F1/465 , H03F3/45766 , H03F2203/45454 , H03F2203/45466 , H03F2203/45504 , H03F2203/45508
摘要： An output driver circuit for an integrated circuit is disclosed, where the output driver drives an output terminal with a high logic level having a voltage limited from the power supply voltage of the integrated circuit. The limited voltage is provided by applying a limited output high voltage to an output buffer, such that the drive signal applied to the gate of the pull-up transistor in the output driver is limited by the limited output high voltage applied to the output buffer. A voltage reference and regulator circuit for generating the limited output high voltage, or for generating a reference voltage for application to a circuit other than an output buffer and that demands sink current, is also disclosed. The voltage reference and regulator is based on a current mirror, in which the sum of the current in the current mirror is controlled by a bias current source which may be dynamically controlled within the operating cycle or programmed by way of fuses. A sink current path circuit, according to various alternatives, is disclosed as providing an additional sink current path in the event that the limited output high voltage, or reference voltage, exceeds the desired level.
摘要翻译：公开了一种用于集成电路的输出驱动器电路，其中输出驱动器以具有限制了集成电路的电源电压的电压的高逻辑电平来驱动输出端子。通过将有限输出高电压施加到输出缓冲器来提供受限电压，使得施加到输出驱动器中的上拉晶体管的栅极的驱动信号受到施加到输出缓冲器的受限输出高电压的限制。还公开了一种电压基准和调节器电路，用于产生受限的输出高电压，或者用于产生用于除了输出缓冲器之外的电路的基准电压并且需要吸收电流。电压参考和调节器基于电流镜，其中电流镜中的电流总和由偏置电流源控制，该偏置电流源可在操作周期内动态控制或通过熔断器进行编程。根据各种备选方案，灌电流路径电路被公开为在受限输出高电压或参考电压超过期望电平的情况下提供附加灌电流路径。

5. 发明公开

EP0718739A3 Voltage reference circuit using an offset compensating current source 失效
标题翻译：电压参考电路使用偏移补偿电流源
公开(公告)号：EP0718739A3
公开(公告)日：1996-07-03
申请号：EP95308560.2
申请日：1995-11-28
申请人： SGS-THOMSON MICROELECTRONICS, INC.
发明人： McClure, David C.
IPC分类号： G05F1/46 , H03F3/45
CPC分类号： H03F3/45766 , G05F1/465 , H03F3/45479 , H03F2203/45454 , H03F2203/45466 , H03F2203/45504 , H03F2203/45508
摘要： An output driver circuit for an integrated circuit is disclosed, where the output driver drives an output terminal with a high logic level having a voltage limited from the power supply voltage of the integrated circuit. The limited voltage is provided by applying a limited output high voltage to an output buffer, such that the drive signal applied to the gate of the pull-up transistor in the output driver is limited by the limited output high voltage applied to the output buffer. A voltage reference and regulator circuit for generating the limited output high voltage is also disclosed, and is based on a current mirror. The sum of the current in the current mirror is controlled by a bias current source, which may be dynamically controlled within the operating cycle or programmed by way of fuses. An offset compensating current source adds current into the reference leg of the current mirror to eliminate the development of an offset voltage in the current mirror, and the limited output high voltage is shifted by the threshold voltage of the pull-up drive transistor by way of a threshold shift circuit.
摘要翻译：公开了一种用于集成电路的输出驱动器电路，其中输出驱动器以具有限制了集成电路的电源电压的电压的高逻辑电平来驱动输出端子。通过将有限输出高电压施加到输出缓冲器来提供受限电压，使得施加到输出驱动器中的上拉晶体管的栅极的驱动信号受到施加到输出缓冲器的受限输出高电压的限制。还公开了用于产生受限输出高电压的电压基准和调节器电路，并基于电流镜。电流镜中电流的总和由偏置电流源控制，该电流源可在工作周期内动态控制或通过熔断器进行编程。偏移补偿电流源将电流添加到电流镜的参考支路中以消除电流镜中的偏移电压的发展，并且限制输出高电压通过上拉驱动晶体管的阈值电压移位一个阈值移位电路。

6. 发明公开

EP2649725A2 FAST POWER UP COMPARATOR 审中-公开
标题翻译： FAST功率比较
公开(公告)号：EP2649725A2
公开(公告)日：2013-10-16
申请号：EP11847138.2
申请日：2011-12-12
申请人： Marvell World Trade Ltd.
发明人： CYRUSIAN, Sasan
IPC分类号： H03F3/45 , H03G3/20
CPC分类号： G06F1/3287 , G06F1/3234 , H03F1/0266 , H03F1/0272 , H03F1/0283 , H03F3/185 , H03F3/2173 , H03F3/2178 , H03F3/3022 , H03F3/3033 , H03F3/45183 , H03F3/4521 , H03F3/45475 , H03F3/72 , H03F2200/03 , H03F2200/264 , H03F2200/27 , H03F2200/321 , H03F2200/75 , H03F2200/78 , H03F2203/45466 , H03F2203/45471 , H03F2203/45504 , H03F2203/45506 , H03F2203/45512 , H03F2203/45674 , H03F2203/45726 , H03F2203/7203
摘要： A circuit method includes periodically increasing a tail current of a differential stage of a comparator to periodically power on the differential stage to a power-on state, and periodically decreasing the tail current of the differential stage to periodically power down the differential stage to a low-power state. The periodically increasing of the tail current and the periodically decreasing of the tail current are asynchronous operations for powering on the differential stage to the power-on state and powering down the differential stage to the low-power state. Periodically increasing the tail current and the periodically decreasing the tail current asynchronously for powering on the differential stage to the power-on state and powering down the differential stage to the low-power state provide for low noise and high speed during signal comparison.

7. 发明公开

EP1835624A3 Power management in a data acquisition system 审中-公开
标题翻译：电源管理在数据采集系统
公开(公告)号：EP1835624A3
公开(公告)日：2009-01-07
申请号：EP07004908.5
申请日：2007-03-09
申请人： Cirrus Logic, Inc.
发明人： Kejariwal, Murari , Coupe, John R.
IPC分类号： H03M1/12 , H03G1/00
CPC分类号： H03F3/45188 , H03F3/45475 , H03F2200/331 , H03F2203/45032 , H03F2203/45371 , H03F2203/45396 , H03F2203/45486 , H03F2203/45504 , H03F2203/45631 , H03F2203/45634 , H03F2203/45726 , H03G1/0029 , H03G1/0088 , H03M1/129
摘要： A data acquisition system (200) includes a programmable gain amplifier (202), an analog-to-digital converter (204), a filter (206), and control circuitry. The programmable gain amplifier (202) is operatively connected to receive an analog input signal on its input (208, 210) and generates an amplified signal on its output (212, 214) in accordance with gain control signals (gc1-gc3). The analog-to-digital converter (204) is operatively connected to receive the amplified signal from the amplifier (202) and generates a digitized signal on its output (216, 218). The filter (206) is operatively connected to receive the digitized signal from the converter (204) and generates a filtered digital signal on its output (220, 222). The control circuitry is operatively connected to the amplifier (202) and to the converter (204) and is also responsive to the gain control signals (gc1-gc3) for dynamically adjusting power between the amplifier and converter when the gain control signals (gc1-gc3) are changed.

8. 发明公开

EP1961115A1 CIRCUIT ELECTRONIQUE A COMPENSATION DE DECALAGE INTRINSEQUE DE PAIRES DIFFERENTIELLES 有权
标题翻译：利用差分对的补偿内在OFFSETS电子电路
公开(公告)号：EP1961115A1
公开(公告)日：2008-08-27
申请号：EP06830542.4
申请日：2006-12-12
申请人： E2V Semiconductors
发明人： BORE, François , BRUEL, Sandrine
IPC分类号： H03F3/45 , H03M3/00
CPC分类号： H03F3/45748 , H03F3/456 , H03F2203/45212 , H03F2203/45352 , H03F2203/45482 , H03F2203/45504 , H03F2203/45512 , H03F2203/45514 , H03M1/445
摘要： The invention relates to analogue integrated electronic circuits using differential pairs (T1, T2). An automatic method of correcting offset voltage is proposed, comprising the following steps: short-circuiting the inputs (V1, V2) of the differential circuit during a calibration phase that is distinct from the normal usage phase; charging a capacitance through the difference in the output currents of the branches of the differential pair in this phase; comparing the voltage across the terminals of the capacitance with at least one threshold; retaining in memory, during the normal usage phase following the calibration phase, the result of the comparison; applying, in the normal usage phase, a correction dependent on the result retained in memory to a current source (SC1, SC2) of a follower stage upstream of the differential pair.

9. 发明公开

EP1748552A1 Current-controlled CMOS (C3MOS) fully differential integrated wideband amplifier/equalizer with adjustable gain and frequency response without additional power or loading 有权
标题翻译：电流控制全差分CMOS宽带带可调频率响应放大器/均衡器在不增加功率消耗
公开(公告)号：EP1748552A1
公开(公告)日：2007-01-31
申请号：EP06008840.8
申请日：2006-04-27
申请人： Broadcom Corporation
发明人： Cao, Jun
IPC分类号： H03F3/45
CPC分类号： H03F3/45183 , H03F3/45197 , H03F2200/405 , H03F2203/45134 , H03F2203/45332 , H03F2203/45466 , H03F2203/45504 , H03F2203/45554 , H03F2203/45638 , H03F2203/45702 , H03G1/0029 , H03G1/0088
摘要： Current-controlled CMOS (C3MOS) fully differential integrated wideband amplifier/equalizer with adjustable gain and frequency response without additional power or loading. A novel approach is presented by which adjustable amplification and equalizer may be achieved using a C3MOS wideband data stage. This may be referred to as a C3MOS wideband data amplifier/equalizer circuit. This employs a wideband differential transistor pair that is fed using two separate transistor current sources. A switchable RC network is communicatively coupled between the sources of the individual transistors of the wideband differential transistor pair. There are a variety of means by which the switchable RC network may be implemented, including using a plurality of components (e.g., capacitors and resistors connected in parallel). In such an embodiment, each component may have an individual switch to govem its connectivity in the switchable RC network thereby allowing a broad range of amplification and equalization to be performed.
摘要翻译：电流控制CMOS（C 3 MOS）完全集成的差分宽带放大器/均衡器具有可调整增益和无需额外的功率或负载的频率响应。的新方法是由可调节的放大和均衡器可以使用C 3个MOS宽带数据的阶段进行呈现。这可以通过对作为一个C 3个MOS宽带数据放大器/均衡器电路被称为。此采用宽带差分晶体管对做了使用两个单独的晶体管的电流源被馈送。一种可切换RC网络可通信地耦合所述宽带差分晶体管对的各个晶体管的源极之间。有各种手段，通过该可开关RC网络可被实现，包括使用（并联连接E.G.，电容器和电阻器）成分的复数。在寻求实施例中，每个部件可以具有切换到个人govem其连接在可切换的RC网络，由此允许一个宽范围的放大和均衡的被执行。

10. 发明公开

EP1560331A1 VARIABLE GAIN AMPLIFIER CIRCUIT AND RADIO MACHINE 审中-公开
标题翻译：可变增益放大器电路和无线电机器
公开(公告)号：EP1560331A1
公开(公告)日：2005-08-03
申请号：EP04702042.5
申请日：2004-01-14
申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
发明人： UDAGAWA, Masaharu
IPC分类号： H03G3/10
CPC分类号： H03G3/001 , H03F2203/45362 , H03F2203/45504 , H03F2203/45616 , H03F2203/7203 , H03G1/0023 , H03G1/0029 , H03G1/0088
摘要： A variable gain amplifier circuit is provided so that an electric current decreases when a voltage gain is lowered and that the amplifier circuit is substantially free of a deterioration in distortion characteristics.
The bases of bipolar transistors Q1, Q3 and Q5 and the bases of bipolar transistors Q2, Q4 and Q6 are connected in common with each other, these bipolar transistors forming a plurality of common-emitter amplifier circuits, and switches SW2, SW1 and SW0 are connected to the respective sides of the bipolar transistors. The emitter sides are held at a ground potential gnd by switching the switches SW2, SW1 and SW0 so that the voltage gain is controlled by selecting the common-emitter amplifier circuits different in voltage gain. A collector current 10 and an emitter degeneration resistance Re between the common-emitter amplifier circuits are so arranged as to have different values. The ratio of the collector current 10 is set inversely proportional to the ratio of the emitter degeneration resistance Re, whereby the collector current 10 decreases when the voltage gain is lowered and a deterioration in distortion characteristics is substantially obviated.
摘要翻译：可变增益放大器电路被设置为使得当电压增益降低时电流减小并且放大器电路基本上没有失真特性的劣化。双极性晶体管Q1，Q3和Q5的基极以及双极性晶体管Q2，Q4和Q6的基极彼此共同连接，这些双极性晶体管形成多个共发射极放大器电路，并且开关SW2，SW1和SW0是连接到双极晶体管的相应侧。通过切换开关SW2，SW1和SW0将发射极侧保持在地电位gnd，从而通过选择电压增益不同的共射极放大器电路来控制电压增益。共射极放大器电路之间的集电极电流10和发射极负反馈电阻Re被设置为具有不同的值。设定集电极电流10的比率与发射极负反馈电阻Re的比率成反比，由此当电压增益降低时集电极电流10减小，并且基本上消除了失真特性的恶化。

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