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1. 发明授权

EP2395668B1 Reconfigurable interleaver comprising reconfigurable counters 有权
标题翻译：可重构交织器可重新配置的计数器
公开(公告)号：EP2395668B1
公开(公告)日：2016-08-17
申请号：EP10165467.1
申请日：2010-06-10
申请人： NXP B.V.
发明人： Engin, Nur
IPC分类号： H03M13/27 , G06F12/00
CPC分类号： H03M13/2789 , H03M13/271 , H03M13/2725 , H03M13/2739 , H03M13/276 , H03M13/2764 , H03M13/2771 , H03M13/2775 , H03M13/6519 , H03M13/6525

2. 发明授权

EP2429084B1 Method and apparatus for a parameterized interleaver design process 有权
标题翻译：对于参数化Verschachtelungsgestaltungsverfahren方法和装置
公开(公告)号：EP2429084B1
公开(公告)日：2013-12-25
申请号：EP11181137.8
申请日：2011-09-13
申请人： Hughes Network Systems, LLC
发明人： Seshadri, Rohit , Eroz, Mustafa , Lee, Lin-Nan
IPC分类号： H03M13/27
CPC分类号： H03M13/2767 , H03M13/275 , H03M13/276 , H03M13/2789
摘要： A parameterized interleaver design process is provided, which optimizes the design for interleavers of any size, and can be completely specified using only a few design parameters. According to the parameterized interleaver design process an interleaver À(i) of a length N is generated. A number of subpermutation masks are defined, and a first intermediate interleaver permutation is partitioned into a number of subgroups, wherein the number of subgroups corresponds with the number of subpermutation masks. Each of the subgroups of the first intermediate interleaver permutation is partitioned into a number of further subgroups, and each of the subpermutation masks is applied to each of the further subgroups of a corresponding subgroup of the first intermediate interleaver permutation, resulting in a corresponding portion of a second intermediate interleaver permutation. The resulting interleaver À(i) is generated based at least in part on the first and second intermediate interleaver permutations.

3. 发明授权

EP1733477B1 SUB-BLOCK INTERLEAVING AND DE-INTERLEAVING FOR MULTIDIMENSIONAL PRODUCT BLOCK CODES 有权
标题翻译：传播与解扩BASIERND在块多维产品分组码
公开(公告)号：EP1733477B1
公开(公告)日：2013-06-19
申请号：EP04821967.9
申请日：2004-04-09
申请人： Agere Systems Inc.
发明人： LIN, Xiaotong
IPC分类号： H03M13/27 , H03M13/29
CPC分类号： H03M13/2764 , H03M13/2703 , H03M13/2721 , H03M13/2757 , H03M13/276 , H03M13/2778 , H03M13/29 , H03M13/2909 , H03M13/2918

4. 发明公开

EP2595320A1 DE-INTERLEAVING DEVICE AND METHOD, AND DATA TRANSMISSION SYSTEM AND METHOD 审中-公开
标题翻译：全球超大型企业
公开(公告)号：EP2595320A1
公开(公告)日：2013-05-22
申请号：EP11806403.9
申请日：2011-01-12
申请人： Panasonic Corporation
发明人： ISHII, Tatsuji c/o Panasonic Corporation
IPC分类号： H03M13/27
CPC分类号： G06F12/0607 , H03M13/2707 , H03M13/276 , H03M13/2764 , H03M13/2789
摘要： An input data block having a variable length is, without an additional memory unit, de-interleaved by using a single memory. A de-interleaving device for de-interleaving an input data block interleaved by storing data of an original data block including RxC' portions (C' represents any divisor of R×C) of data in a matrix of R columns × C rows in row-major order and reading the data of the original data block in column-major order includes a memory (11) configured to store R×C portions of data, a write address generator (12) configured to generate write addresses based on a first incremental value, a read address generator (13) configured to generate read addresses other than other than (n×R)+1th read addresses based on the first incremental value and to generate the (n×R)+1th read addresses based on a second incremental value, and a memory interface (14) configured to successively read data from a read address and to successively write data of an input data block to a write address.
摘要翻译：具有可变长度的输入数据块，没有附加存储器单元，通过使用单个存储器进行解交织。一种解交织装置，用于通过将包括R列的数据块（C'表示R×C的任何除数）的原始数据块的数据以行R列×C行的矩阵的形式进行交织，主要命令并以列主要顺序读取原始数据块的数据包括被配置为存储数据的R×C部分的存储器（11），写地址生成器（12），其被配置为基于第一增量生成写入地址值，读地址生成器（13），被配置为基于第一增量值生成除（n×R）+第1读取地址以外的读取地址，并且基于第二增益值生成（n×R）+第1读取地址增量值和存储器接口（14），其被配置为从读取地址连续地读取数据，并且将输入数据块的数据顺序地写入到写入地址。

5. 发明公开

EP2173036A3 Turbo code interleaver with near optimal performance 有权
标题翻译：交织器涡轮代码annäherender最佳性能下
公开(公告)号：EP2173036A3
公开(公告)日：2013-03-06
申请号：EP09015143.2
申请日：1999-08-16
申请人： Hughes Electronics Corporation
发明人： Eroz, Mustafa , Hammons, A., Roger, Jr. , Sun, Feng-Wen
IPC分类号： H03M13/27 , H03M13/29
CPC分类号： H03M13/271 , H03M13/2735 , H03M13/2746 , H03M13/276 , H03M13/2767 , H03M13/2771 , H03M13/2789 , H03M13/2957
摘要： A method of interleaving blocks of indexed data of varying length is disclosed. The method includes the steps of: providing a set of basic Interleavers comprising a family of one or more permutations of the indexed data and having a variable length; selecting one of the basic Interleavers based upon a desired Interleaver length L; and adapting the selected basic Interleaver to produce an Interleaver having the desired Interleaver length L.

6. 发明公开

EP2466472A1 Vector-based matching circuit for data streams 审中-公开
标题翻译： Vektorbasierte AnpassungsschaltungfürDatenströme
公开(公告)号：EP2466472A1
公开(公告)日：2012-06-20
申请号：EP10195792.6
申请日：2010-12-17
申请人： ST-Ericsson SA
发明人： Rijshouwer, Erik , Van Berkel, Cornelis
IPC分类号： G06F12/06
CPC分类号： G06F3/0604 , G06F3/0656 , G06F3/0671 , G06F12/0607 , H03M13/2757 , H03M13/276
摘要： Systems and methods are described relating to a matcher that inputs partial vectors at a rate of 1 per clock cycle and delivers complete vectors at the output with an indication per vector of its validity. The matcher can copy a maximum number of valid elements from an input queue to target vector in-order each clock cycle and eliminate copied elements from the input queue. The completely filled target vectors are paired with the complete data vectors and outputted as composite vectors.
摘要翻译：描述了与以每个时钟周期为1的速率输入部分向量的匹配器相关联的系统和方法，并且在输出端传递完整的向量，其中每个向量的有效性指示。匹配器可以将输入队列中的最大数量的有效元素从每个时钟周期顺序复制到目标向量，并从输入队列中消除复制的元素。完全填充的目标矢量与完整的数据矢量配对并作为复合矢量输出。

7. 发明公开

EP2429084A1 Method and apparatus for a parameterized interleaver design process 有权
标题翻译：对于参数化Verschachtelungsgestaltungsverfahren方法和装置
公开(公告)号：EP2429084A1
公开(公告)日：2012-03-14
申请号：EP11181137.8
申请日：2011-09-13
申请人： Hughes Network Systems, LLC
发明人： Seshadri, Rohit , Eroz, Mustafa , Lee, Lin-Nan
IPC分类号： H03M13/27
CPC分类号： H03M13/2767 , H03M13/275 , H03M13/276 , H03M13/2789
摘要： A parameterized interleaver design process is provided, which optimizes the design for interleavers of any size, and can be completely specified using only a few design parameters. According to the parameterized interleaver design process an interleaver π(i) of a length N is generated. A number of subpermutation masks are defined, and a first intermediate interleaver permutation is partitioned into a number of subgroups, wherein the number of subgroups corresponds with the number of subpermutation masks. Each of the subgroups of the first intermediate interleaver permutation is partitioned into a number of further subgroups, and each of the subpermutation masks is applied to each of the further subgroups of a corresponding subgroup of the first intermediate interleaver permutation, resulting in a corresponding portion of a second intermediate interleaver permutation. The resulting interleaver π(i) is generated based at least in part on the first and second intermediate interleaver permutations.

8. 发明公开

EP2306654A3 Turbo decoding device and communication device 审中-公开
标题翻译： turbo解码装置和通信装置
公开(公告)号：EP2306654A3
公开(公告)日：2011-04-13
申请号：EP10176753.1
申请日：2010-09-15
申请人： Fujitsu Limited
发明人： IMAFUKU, Kazuaki , OBUCHI, Kazuhisa , MIYAZAKI, Shunji , YAMADA, Hideaki , SAITO, Mutsumi , INOUE, Masaru , HOTTA, Shingo
IPC分类号： H03M13/29 , H03M13/27
CPC分类号： H03M13/2957 , H03M13/276 , H03M13/2775 , H03M13/6525 , H03M13/6566
摘要： A turbo decoding device (100) includes a memory unit (101) that stores data in an interleaving process performed in a process of decoding a coded signal encoded with a turbo code and an access unit (102) that accesses the memory unit (101) to read and write the data. The memory unit (101) includes memory circuits and is formed as one memory space by coupling the memory circuits. Furthermore, the memory circuit functions as a first bank configuration by which a first capacity is assigned to each bank or a second bank configuration by which a second capacity is assigned to each bank in accordance with a combination of the memory circuits. Moreover, the access unit (102) selects by which of the first bank configuration and the second bank configuration the memory unit (101) functions in accordance with a communication method of a coded signal and accesses the memory unit (101) in accordance with the selected bank configuration.

9. 发明公开

EP2204002A1 DATA PROCESSING APPARATUS AND METHOD 有权
标题翻译：装置和方法用于数据处理
公开(公告)号：EP2204002A1
公开(公告)日：2010-07-07
申请号：EP08843411.3
申请日：2008-10-24
申请人： Sony Corporation
发明人： ATUNGSIRI, Samuel, Asanbeng , TAYLOR, Matthew, Paul, Athol , WILSON, John, Nicholas
IPC分类号： H04L1/00 , H04L27/26 , H03M13/27
CPC分类号： H04L5/0007 , G11C19/00 , H03M13/276 , H04L1/0071 , H04L5/0053 , H04L27/14 , H04L27/2602 , H04L27/2647
摘要： A data processing apparatus maps input symbols to be communicated onto a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol. The data processor includes an interleaver memory which reads-in the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals. The interleaver memory reads-out the data symbols on to the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on to the sub-carrier signals. The set of addresses are generated from an address generator which comprises a linear feedback shift register and a permutation circuit.

10. 发明授权

EP1949550B1 A METHOD AND APPARATUS FOR GENERATING A PERMUTATION FOR REVERSE LINK HOPPING IN WIRELESS COMMUNICATION SYSTEM 有权
标题翻译：方法和设备，用于生成改弦易辙JUMP排序为无线通信系统
公开(公告)号：EP1949550B1
公开(公告)日：2010-05-19
申请号：EP06826821.8
申请日：2006-10-27
申请人： QUALCOMM Incorporated
发明人： PALANKI, Ravi , KHANDEKAR, Aamod
IPC分类号： H04B1/713 , H04L27/26
CPC分类号： H04L5/0041 , H03M13/2725 , H03M13/276 , H03M13/2789 , H03M13/2957 , H04B1/7143 , H04J13/00 , H04L1/0003 , H04L1/0026 , H04L1/0625 , H04L5/0007 , H04L5/0026 , H04L5/005 , H04L25/0228 , H04L27/2602 , H04W52/54

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