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1. 发明公开

EP2118902A1 METHODS AND APPARATUS FOR CLOCK SIGNAL SYNCHRONIZATION IN A CONFIGURATION OF SERIES-CONNECTED SEMICONDUCTOR DEVICES 有权
标题翻译：针对系列中配置时钟信号同步方法和设备转换的半导体布置
公开(公告)号：EP2118902A1
公开(公告)日：2009-11-18
申请号：EP08714560.3
申请日：2008-02-05
申请人： Mosaid Technologies Incorporated
发明人： OH, HakJune
IPC分类号： G11C8/18 , G06F1/10 , G11C19/00 , G11C8/12
CPC分类号： G11C19/00 , G06F1/10 , H03L7/0812
摘要： A system includes a system controller and a configuration of series-connected semiconductor devices. Such a device includes an input for receiving a clock signal originating from a previous device, and an output for providing a synchronized clock signal destined for a succeeding device. The device further includes a clock synchronizer for producing the synchronized clock signal by processing the received clock signal and an earlier version of the synchronized clock signal. The device further includes a device controller for adjusting a parameter used by the clock synchronizer in processing the earlier version of the synchronized clock signal. The system controller has an output for providing a first clock signal to a first device, and an input for receiving a second clock signal from a second device. The second clock signal corresponds to a version of the first clock signal that has undergone processing by a clock synchronizer in at least one of the devices. The system controller further includes a detector for processing the first and second clock signals to detect a phase difference therebetween; and a synchronization controller for commanding an adjustment to the clock synchronizer in at least one of the devices based on the phase difference detected by the detector.

2. 发明公开

EP2021930A1 APPARATUS AND METHOD FOR ESTABLISHING DEVICE IDENTIFIERS FOR SERIALLY INTERCONNECTED DEVICES 审中-公开
标题翻译：设备和方法设置设备标识符SERIAL共享ASSOCIATES
公开(公告)号：EP2021930A1
公开(公告)日：2009-02-11
申请号：EP07719813.3
申请日：2007-05-18
申请人： Mosaid Technologies Incorporated
发明人： PYEON, Hong Beom , OH, HakJune , KIM, Jin-Ki
IPC分类号： G06F13/00 , G06F13/42
CPC分类号： G06F13/4256 , G06F2213/0052
摘要： A method or apparatus operates a multitude of devices in a serial interconnection configuration to establish a device identifier (ID) for each device. An input signal is transmitted through a serial interconnection to a first device using inputs that are also used by the first device to input other information thereto (e.g., data, commands, control signals). A generating circuit generates a device ID in response to the input signal. A transfer circuit then transfers an output signal associated with the device ID to a second device through a serial output of the first device. The serial output is also used by the first device to output other information (e.g., signals, data) to another device in the serial interconnection configuration.

3. 发明授权

EP2118902B1 METHODS AND APPARATUS FOR CLOCK SIGNAL SYNCHRONIZATION IN A CONFIGURATION OF SERIES-CONNECTED SEMICONDUCTOR DEVICES 有权
标题翻译：针对系列中配置时钟信号同步方法和设备转换的半导体布置
公开(公告)号：EP2118902B1
公开(公告)日：2012-07-18
申请号：EP08714560.3
申请日：2008-02-05
申请人： Mosaid Technologies Incorporated
发明人： OH, HakJune
IPC分类号： G11C8/18 , G06F1/10 , G11C19/00 , G11C8/12 , H03L7/081
CPC分类号： G11C19/00 , G06F1/10 , H03L7/0812
摘要： A system includes a system controller and a configuration of series-connected semiconductor devices. Such a device includes an input for receiving a clock signal originating from a previous device, and an output for providing a synchronized clock signal destined for a succeeding device. The device further includes a clock synchronizer for producing the synchronized clock signal by processing the received clock signal and an earlier version of the synchronized clock signal. The device further includes a device controller for adjusting a parameter used by the clock synchronizer in processing the earlier version of the synchronized clock signal. The system controller has an output for providing a first clock signal to a first device, and an input for receiving a second clock signal from a second device. The second clock signal corresponds to a version of the first clock signal that has undergone processing by a clock synchronizer in at least one of the devices. The system controller further includes a detector for processing the first and second clock signals to detect a phase difference therebetween; and a synchronization controller for commanding an adjustment to the clock synchronizer in at least one of the devices based on the phase difference detected by the detector.

4. 发明公开

EP2183748A1 DAISY-CHAIN MEMORY CONFIGURATION AND USAGE 审中-公开
标题翻译： DAISY连锁店的配置和使用
公开(公告)号：EP2183748A1
公开(公告)日：2010-05-12
申请号：EP08783415.6
申请日：2008-08-27
申请人： Mosaid Technologies Incorporated
发明人： OH, HakJune
IPC分类号： G11C7/10 , G11C29/52
CPC分类号： G06F13/426 , G06F11/1068 , G06F13/1684 , G11C7/1006 , G11C2029/0411 , Y02D10/14 , Y02D10/151
摘要： Daisy-chain memory configuration and usage is disclosed. According to one configuration, a memory system includes a controller and corresponding string of multiple successive memory devices coupled in a daisy-chain manner. The controller communicates commands over the serial control link to configure a first memory device to write a block of data to a second memory device in the chain. For example, the controller initiates copying a block of data by communicating over the daisy-chain control link to configure a first memory device of the multiple memory devices to be a source for outputting data, communicating over the daisy-chain control link to configure a second memory device to be a destination for receiving data, and communicating over the daisy-chain control link to initiate a transfer of the data from the first memory device to the second memory device.

5. 发明公开

EP2126918A1 INDEPENDENT LINK AND BANK SELECTION 审中-公开
标题翻译：独立的银行连接和选择
公开(公告)号：EP2126918A1
公开(公告)日：2009-12-02
申请号：EP07855602.4
申请日：2007-12-21
申请人： Mosaid Technologies Incorporated
发明人： PYEON, Hong, Beom , OH, HakJune , KIM, Jin-Ki
IPC分类号： G11C8/12 , G11C29/26
CPC分类号： G06F13/4022 , G11C7/1048 , G11C7/18 , G11C11/408
摘要： Provided is a memory system that has a plurality of memory banks and a plurality of link controllers. For each memory bank, there is first switching logic for receiving output for each link controller, and for passing on the output of only one of the link controllers to the memory bank. For each link controller, there is second switching logic for receiving an output of each memory bank, and for passing on the output of only one of the memory banks to the link controller. According to an embodiment of the invention, there is switch controller logic for controlling operation of both the first switching logic and the second switching logic to prevent simultaneous or overlapping access by multiple link controllers to the same memory bank, and for preventing simultaneous or overlapping access to multiple banks by the same link controller.

6. 发明公开

EP2016588A1 DYNAMIC RANDOM ACCESS MEMORY WITH FULLY INDEPENDENT PARTIAL ARRAY REFRESH FUNCTION 审中-公开
标题翻译：动态随机存取存储器完全自主PARTIALARRAY刷新
公开(公告)号：EP2016588A1
公开(公告)日：2009-01-21
申请号：EP07719431.4
申请日：2007-03-28
申请人： Mosaid Technologies Incorporated
发明人： KIM, Jin-Ki , OH, HakJune
IPC分类号： G11C11/406 , G11C11/403 , G11C8/12
CPC分类号： G11C11/40615 , G11C11/406 , G11C11/40607 , G11C11/40618 , G11C11/40622
摘要： A dynamic random access memory device includes a plurality of memory subblocks. Each subblock has a plurality of wordlines whereto a plurality of data store cells are connected. Partial array self-refresh (PASR) configuration settings are independently made. In accordance with the PASR settings, the memory subblocks are addressed for refreshing. The PASR settings are made by a memory controller. Any kind of combinations of subblock addresses may be selected. Thus, the memory subblocks are fully independently refreshed. User selectable memory arrays for data retention provide effective memory control programming especially for low power mobile application.

7. 发明公开

EP1929480A1 DAISY CHAIN CASCADING DEVICES 有权
标题翻译： DAISY链式连接器
公开(公告)号：EP1929480A1
公开(公告)日：2008-06-11
申请号：EP06790771.7
申请日：2006-09-29
申请人： Mosaid Technologies Incorporated
发明人： PYEON, Hong, Beom , KIM, Jin-Ki , OH, HakJune
IPC分类号： G11C7/10 , G11C11/4197 , G11C16/06
CPC分类号： G11C7/10 , G06F12/0623 , G06F13/4247 , G06F13/4256 , G11C5/066 , G11C16/06
摘要： A technique for serially coupling devices in a daisy chain cascading arrangement. Devices are coupled in a daisy chain cascade arrangement such that outputs of a first device are coupled to inputs of a second device later in the daisy chain to accommodate the transfer of information, such as data, address and command information, and control signals to the second device from the first device. The devices coupled in the daisy chain comprise a serial input (SI) and a serial output (SO). Information is input to a device via the SI. The information is output from the device via the SO. The SO of an earlier device in the daisy chain cascade is coupled to the SI of a device later in the daisy chain cascade. Information input to the earlier device via the device's SI is passed through the device and output from the device via the device's SO. The information is then transferred to the later device's SI via the connection from the earlier device's SO and the later device's SI.
摘要翻译：串联耦合设备的技术，采用菊花链级联布置。设备以菊花链级联布置耦合，使得第一设备的输出在菊花链中稍后耦合到第二设备的输入以适应信息（诸如数据，地址和命令信息以及控制信号）向来自第一设备的第二设备。耦合在菊花链中的器件包括串行输入（SI）和串行输出（SO）。信息通过SI输入到设备。信息通过SO从设备输出。菊花链级联中的较早器件的SO在菊花链级联中稍后与器件的SI相耦合。通过设备的SI输入到较早设备的信息通过设备并通过设备的SO从设备输出。然后通过来自早期设备的SO和后面的设备的SI的连接将信息传送到更晚的设备的SI。

8. 发明授权

EP2126915B1 MEMORY SYSTEM AND METHOD WITH SERIAL AND PARALLEL MODES 有权转让
标题翻译：内存系统和方法串行和并行模式
公开(公告)号：EP2126915B1
公开(公告)日：2014-02-19
申请号：EP07855504.2
申请日：2007-12-10
申请人： Mosaid Technologies Incorporated
发明人： PYEON, Hong Beom , OH, HakJune , KIM, Jin-Ki
IPC分类号： G11C7/10 , G11C11/34 , H03M9/00
CPC分类号： G11C7/1045 , G11C7/1006 , G11C7/1051 , G11C7/1075 , G11C7/1078 , G11C2207/107

9. 发明公开

EP2329496A1 SERIAL-CONNECTED MEMORY SYSTEM WITH OUTPUT DELAY ADJUSTMENT 审中-公开
标题翻译：串行交换存储系统具有输出延迟设置
公开(公告)号：EP2329496A1
公开(公告)日：2011-06-08
申请号：EP09817125.9
申请日：2009-09-17
申请人： MOSAID Technologies Incorporated
发明人： OH, HakJune
IPC分类号： G11C7/22 , G11C16/32 , G11C5/02
CPC分类号： G11C7/22 , G11C7/1066 , G11C7/1069 , G11C7/222 , G11C16/32
摘要： Systems and methods for correcting clock duty cycle and/or performing output delay adjustment are provided for application in serial- connected devices operating as slave devices. A master device provides a clock to the first slave device. Each slave device passes the clock to the next slave device in turn. The last slave device returns the clock to the master device. The master device compares the outgoing and returned clocks and determines if a duty cycle correction and/or an output delay adjustment is needed. If so, the master device generates and outputs commands for slave devices to perform duty cycle and/or output delay adjustment. The slave devices each have a circuit for performing duty cycle correction and/or output delay adjustment. In some implementations, each slave device is a memory device, and the master device is a memory controller.

10. 发明公开

EP2126916A2 SYSTEM HAVING ONE OR MORE MEMORY DEVICES 审中-公开
标题翻译：与一个或多个存储设备系统
公开(公告)号：EP2126916A2
公开(公告)日：2009-12-02
申请号：EP08730166.9
申请日：2008-02-19
申请人： Mosaid Technologies Incorporated
发明人： OH, HakJune , PRZYBYLSKI, Steven , PYEON, Hong, Beom , SCHUETZ, Roland
IPC分类号： G11C7/10
CPC分类号： G11C7/1045 , G06F13/1678 , G11C7/10 , Y02D10/14
摘要： A system including a memory system and a memory controller is connected to a host system. The memory system has at least one memory device storing data. The controller translates the requests from the host system to one or more separatable commands interpretable by the at least one memory device. Each command has a modular structure including an address identifier for one of the at least one memory devices and a command identifier representing an operation to be performed by the one of the at least one memory devices. The at least one memory device and the controller are in a series-connection configuration for communication such that only one memory device is in communication with the controller for input into the memory system. The memory system can include a plurality of memory devices connected to a common bus.

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