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    • 1. 发明公开
    • Handover in sectorized radiocells
    • Wekrereungung在sektorisierten Funkzellen
    • EP0932319A2
    • 1999-07-28
    • EP99101224.6
    • 1999-01-22
    • MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    • Asano, Nobuo
    • H04Q7/38
    • H04W16/28H04W16/24H04W36/30
    • A base station apparatus measures the statistic of a reported known reference signal with receivable level from another base station, refers to the reported angle difference information and located base station information with respect to the known reference signal of another base station showing the receivable level in a predetermined period, detects a location of the cell with the known reference signal, and when it is determined that the cell is not appropriate for the cell for a handover, outputs an interference degree notification signal to the another base station of that cell. In addition, in the case where it is notified that interference to a certain cell is large by the interference degree notification signal, the notified base station controls to decrease an antenna directivity toward the direction to the certain cell based on the located base station information.
    • 基站装置利用来自另一个基站的可接收等级的报告的已知参考信号的统计量,参照所报告的角度差信息和相对于另一基站的已知参考信号的位置信息, 以预定的周期检测具有已知参考信号的小区的位置,并且当确定该小区不适用于切换的小区时,向该小区的另一个基站输出干扰度通知信号。 此外,在通知干扰度通知信号通知特定小区的干扰较大的情况下,所通知的基站基于所定位的基站信息来控制向朝向该小区的方向的天线方向性的降低。
    • 6. 发明公开
    • Receiving portion of radio communication device
    • Empfangsteil einesKommunikationsgerätes
    • EP0851593A2
    • 1998-07-01
    • EP97309449.3
    • 1997-11-24
    • MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    • Asano, Nobuo
    • H04B1/16
    • H04W52/029H03L1/00H03L7/00H04B2201/70709H04W52/0283Y02D70/00
    • A receiving portion of a radio communication device includes a circuit periodically moving into a sleep mode of operation. The circuit periodically moves out of the sleep mode of operation in response to a re-activation signal. A first clock signal is generated. Clock pulses in the first clock signal are counted. The re-activation signal is generated each time the number of the counted clock pulses in the first clock signal reaches an updatable number. A second clock signal is generated which has a frequency higher than a frequency of the first clock signal. Clock pulses in the second clock signal are counted during every time interval determined by the first clock signal. An error of the frequency of the first clock signal with respect to the frequency of the second clock signal is calculated on the basis of a result of the counting of clock pulses in the second clock signal. The updatable number is set in response to the calculated error of the frequency of the first clock signal.
    • 无线电通信设备的接收部分包括周期性地进入睡眠操作模式的电路。 响应于重启信号,电路周期性地移出睡眠操作模式。 产生第一个时钟信号。 第一个时钟信号中的时钟脉冲被计数。 每当第一时钟信号中计数的时钟脉冲的数量达到可更新数量时,就产生重新激活信号。 生成具有高于第一时钟信号的频率的频率的第二时钟信号。 在由第一时钟信号确定的每个时间间隔期间,对第二时钟信号中的时钟脉冲进行计数。 基于第二时钟信号中的时钟脉冲的计数结果计算第一时钟信号相对于第二时钟信号的频率的频率的误差。 响应于计算出的第一时钟信号的频率误差来设定可更新号码。
    • 9. 发明公开
    • Method and system for address access
    • Verfahren und System zum Addressenzugriff。
    • EP0635782A1
    • 1995-01-25
    • EP94305259.7
    • 1994-07-18
    • MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    • Saito, YoshikoUesugi, MitsuruAsano, NobuoIshikawa, Toshihiro
    • G06F7/50G06F5/06G06F12/02G06F9/355
    • G06F7/5055G06F5/10G06F7/505G06F9/3552G06F12/0223G06F2205/106G06F2207/382
    • Different multi-bit addresses extending from a stating address to an ending address are sequentially assigned to respective memory segments in a designated area of a memory which stores data. A fixed-value register stores fixed-value data representative of a predetermined unit address increment, and outputs the fixed-value data. A multi-bit adder adds output data from an address pointer register and the output fixed-value data from the fixed-value register, and outputs data representative of a result of the addition. The address pointer register stores starting-address data representative of the starting address and outputs the starting-address data to the memory and the adder during an initial stage. The address pointer register stores the output data from the adder and outputs the stored data to the memory and the adder during a stage following the initial stage. The adder includes adding circuit elements corresponding to respective bits. In the adder, propagation of a carry from a given one of the adding circuit elements to a subsequent one of the adding circuit elements is inhibited so that an address represented by the output data from the adder returns from the ending address to the starting address when an address represented by the output data from the address pointer register reaches the ending address.
    • 从指定地址延伸到结束地址的不同的多位地址被依次分配给存储数据的存储器的指定区域中的相应存储器段。 固定值寄存器存储表示预定单位地址增量的固定值数据,并输出固定值数据。 多位加法器从地址指针寄存器和固定值寄存器的输出固定值数据中加入输出数据,并输出表示相加结果的数据。 地址指针寄存器存储表示起始地址的起始地址数据,并且在初始阶段将起始地址数据输出到存储器和加法器。 地址指针寄存器存储来自加法器的输出数据,并且在初始阶段之后的阶段将存储的数据输出到存储器和加法器。 加法器包括加上与各个位对应的电路元件。 在加法器中,禁止从相加电路元件中的给定一个加法电路元件的进位到后一个加法电路元件的传播,使得来自加法器的输出数据所表示的地址从结束地址返回到起始地址,当 由地址指针寄存器的输出数据表示的地址到达结束地址。