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1. 发明公开

EP0861491A4 METHOD AND SYSTEM FOR SOFT PROGRAMMING ALGORITHM 失效
标题翻译：系统和方法进行软编程算法研究
公开(公告)号：EP0861491A4
公开(公告)日：2001-03-07
申请号：EP95942436
申请日：1995-11-17
申请人： MACRONIX INT CO LTD , YIU TOM DANG HSING
发明人： YIU TOM DANG-HSING , SHONE FUCHIA , LEE I-LONG , CHEN CHIA-SHING , CHEN HUN-SONG , LIU YUAN-CHANG , SHIAU TZENG-HUEI , CHANG KUEN-LONG , WAN RAY-LIN
IPC分类号： G11C16/34 , G11C7/00
CPC分类号： G11C16/3409 , G11C16/3404
摘要： A floating gate memory device which includes control circuits (2, 3, 4) to generate a repair pulse to repair over-erased cells so they may be repaired block-by-block (1). This invention includes repairing the cells by applying a repair pulse to the cell's bit line (10, 11) while maintaining the word line voltage above ground. In a different embodiment, the word line voltage is maintained at two different voltage levels above ground. In the first stage, the word line voltage is maintained between approximately 0.1 volts and 0.2 volts for approximately 100 ms while the repair pulse is applied. In the second stage, the word line voltage is maintained between approximately 0.4 volts and 0.5 volts for approximately 100 ms while the repair pulse is applied.

2. 发明公开

EP1058930A4 A MEMORY SUPPORTING MULTIPLE ADDRESS PROTOCOLS 失效
标题翻译：对记忆支持多种地址协议
公开(公告)号：EP1058930A4
公开(公告)日：2005-02-16
申请号：EP98901220
申请日：1998-01-06
申请人： MACRONIX INT CO LTD
发明人： CHEN HAN SUNG , SHIAU TZENG-HUEI , CHANG TSO-MING , WAN RAY-LIN , SHONE FUCHIA
IPC分类号： G11C16/06 , G06F9/445 , G06F12/00 , G06F12/02 , G11C8/00 , G11C16/08 , G11C16/10
CPC分类号： G06F9/4403 , G11C8/00 , G11C16/08 , G11C16/10
摘要： The present invention provides a new memory device for storage of boot code for microprocessors. The device includes a memory array (130), a first block, and decoders (118, 120). The first block is defined as rows of the memory array. The decoders decode a memory access request for the data. The memory access request may be either one of a top-down or bottom-up address protocol. In another embodiment, an integrated circuit memory includes: a memory array (130), a decoder, a control (136), and a logic gate (132). The decoders select a row of the memory array. The control outputs either a bottom-up or a top-down address protocol signal. The logic gate outputs a logical 'Exclusive Or' of the control signal and a corresponding bit of the memory request, whereby a memory request in a bottom-up address protocol is converted to a memory address in a top-down address protocol.

3. 发明公开

EP0904587A4 PAGE MODE FLOATING GATE MEMORY DEVICE STORING MULTIPLE BITS PER CELL 失效
标题翻译： PAGE MODE浮栅存储器用协议MEHRBITZELLEN
公开(公告)号：EP0904587A4
公开(公告)日：1999-05-19
申请号：EP96921627
申请日：1996-06-14
申请人： MACRONIX INT CO LTD
发明人： HUNG CHUN-HSIUNG , WAN RAY-LIN , CHENG YAO-WU
IPC分类号： G11C16/06 , G11C11/56 , G11C16/02 , G11C16/10 , G11C16/34 , G11C7/00 , G11C8/00
CPC分类号： G11C16/3445 , G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C16/10 , G11C16/3436 , G11C16/3459 , G11C2211/5622 , G11C2211/5642 , G11C2216/14
摘要： An array (10) of multi-level floating gate memory cells includes wordlines (18) connected to memory cells along a row in the array, and bit lines (12) connected to memory cells along a column in the array. A wordline voltage source (27) is included which supplies selectively wordline voltages corresponding to respective threshold voltages of the memory cells in the array. A plurality of bit latches form a page buffer (11). Bit latches are coupled to corresponding bit lines, and have a first state and a second state. The bit latches include circuits (213-216) to change the bit latches from the first state to the second state in response to signals on the corresponding bit lines that are generated in response to a wordline voltage on a selected wordline being greater than or equal to the threshold voltage of a memory cell on the corresponding bit line connected to the selected wordline. Logic (21) controls the wordline voltage source and the bit latches to apply in a sequence the wordline voltages, and to sense the state of the bit latches after applying each wordline voltage in the sequence to determine the threshold voltages of the memory cells.

4. 发明公开

EP1002320A4 BLOCK DECODED WORDLINE DRIVER WITH POSITIVE AND NEGATIVE VOLTAGE MODES USING FOUR TERMINAL MOS TRANSISTORS 失效
标题翻译：具有正负电压操作使用MOS晶体管，四个端口BLOCKDEKODIERTER字线驱动器
公开(公告)号：EP1002320A4
公开(公告)日：2003-05-07
申请号：EP98926353
申请日：1998-06-04
申请人： MACRONIX INT CO LTD
发明人： SHIAU TZENG-HUEI , LIN YU-SHEN , WAN RAY-LIN
IPC分类号： G11C16/02 , G11C8/08 , G11C16/08 , G11C16/04 , G11C7/00 , G11C16/06
CPC分类号： G11C8/08 , G11C16/08
摘要： The negative supply voltage (317) and isolation well bias (320) used by the wordline drivers (306) during erase are decoded separately from the decoding of the inputs of the individual wordline drivers. The wordline drivers selectively drive wordlines with a wordline voltage from either a first supply voltage source or a second supply voltage source in response to address signals which identify the respective drivers. The second supply voltage source includes a set of supply voltage selectors (302, 319). Each supply voltage selector in the set is coupled with a subset of the set of drivers.

5. 发明公开

EP1159659A4 FOUR-PHASE CHARGE PUMP WITH LOWER PEAK CURRENT 有权
标题翻译：与峰值功率低的四相电荷泵
公开(公告)号：EP1159659A4
公开(公告)日：2002-05-15
申请号：EP99905655
申请日：1999-02-02
申请人： MACRONIX INT CO LTD
发明人： LIN YU SHEN , HUNG CHUN-HSIUNG , WAN RAY-LIN
IPC分类号： H01L27/04 , H01L21/822 , H02M3/07 , G05F1/10 , G05F3/20 , G05F3/24 , H03K17/16
CPC分类号： H02M3/073 , H02M2003/075
摘要： A four-phase charge pump circuit suitable for use on integrated circuits includes circuitry (900) that drives charge pum p nodes in two components separated by a time delay. A capacitor connected to a node (722) is pumped low by an inverter and then by a transistor after a certain delay.

6. 发明公开

EP1151365A4 RAPID ON CHIP VOLTAGE GENERATION FOR LOW POWER INTEGRATED CIRCUITS 有权
标题翻译： FAST发电机对集成电路的低功率芯片
公开(公告)号：EP1151365A4
公开(公告)日：2002-01-30
申请号：EP98960305
申请日：1998-11-18
申请人： MACRONIX INT CO LTD
发明人： CHANG KUEN-LONG , HUNG CHUN-HSIUNG , CHEN KEN-HUI , HO TIEN-SHIN , LEE I-LONG , SHIAU TZENG-HEI , WAN RAY-LIN
IPC分类号： G11C11/413 , B60K20/00 , C08G59/06 , F02M61/10 , G05F20060101 , G05F1/10 , G05F1/46 , G05F3/02 , G05F3/20 , G11C5/14 , G11C11/407 , G11C16/06 , H01L21/822 , H01L27/02 , H01L27/04
CPC分类号： G05F1/46
摘要： An on chip voltage generation circuit is provided for use on integrated circuits such as flash memory devices with a low power supply voltage. The voltage generation circuit comprises first and second level detectors (209 and 210) and a boost driver (204), wherein the voltage generation circuit pumps charge at first and second rates in response to outputs of the detectors.

7. 发明公开

EP0876708A4 AN ADDRESS TRANSITION DETECTION CIRCUIT 失效
标题翻译：地址变换检测电路
公开(公告)号：EP0876708A4
公开(公告)日：2000-05-24
申请号：EP96941480
申请日：1996-11-26
申请人： MACRONIX INT CO LTD
发明人： LIU YIN-SHANG , CHANG KUEN-LONG , HUNG CHUN-HSIUNG , CHUANG WEITONG , WAN RAY-LIN
IPC分类号： G11C11/41 , G11C7/22 , G11C8/18 , H03K5/1534 , H03K19/003
CPC分类号： H03K5/1534 , G11C7/22 , G11C8/18
摘要： An address transition detection (ATD) circuit comprises a first (102) and a second (DDS) circuit and an interval timer (300). First circuit (102) receives on a first input (1-1) a change signal corresponding to a transition on one or more address bus lines, and in response transitions the output (O) from a first state to a second state. First circuit (102) receives a reset signal at a second input (1-2) to return the output (O) to the first state. The interval timer (300) has an output coupled to the second input (1-2) of the first circuit (102) and, upon receiving a signal at its input, generates the reset signal at its output after a timed interval. The second circuit (DDS) couples the change signal to the input of the interval timer (300).

8. 发明公开

EP1046121A4 AUTOMATIC TEST PROCESS WITH NON-VOLATILE RESULT TABLE STORE 失效
标题翻译：具有非易失性存储器成绩表自动测试程序
公开(公告)号：EP1046121A4
公开(公告)日：2004-04-21
申请号：EP97911652
申请日：1997-10-08
申请人： MACRONIX INT CO LTD
发明人： WAN RAY-LIN , HUNG CHUN-HSIUNG , SHIAU TZENG-HUEI
IPC分类号： G11C17/00 , G06F3/06 , G06F11/00 , G06G7/64 , G06G7/66 , G11C16/02 , G11C29/12 , G11C29/44 , G11C29/00
CPC分类号： G11C29/44 , G06F11/006
摘要： A method of manufacturing integrated circuits based on providing a test column of memory cells in the devices. A test control processor (100) and a test board (101) for gang testing of integrated circuits (00, 01, 10, 11, 20, ...). Cells in the test column are selected by a portion of the addresses which identifies a row in the main array on the device. A test is executed to determine a characteristic of the device and the results of that test are mapped to the portion of the address which identifies a row in the array. This produces a characteristic code address for the device which indicates the test results of the test. Access to the test column on the device is enabled and a bit is written in response to the characteristic code address in a memory cell on the test column. During manufacture the test column is read in order to classify the device according to the characteristic. This allows for storing in a look up format significant amounts of data about the characteristics of the device without requiring large amounts of memory on the device, and substantially relieving the testing system of a requirement for memory resources.

9. 发明公开

EP1012846A4 CHANNEL FN PROGRAM/ERASE RECOVERY SCHEME 失效
标题翻译： FN-KANAL PROGRAMIERER-LÖSCHWIEDERHERSTELLUNGSSCHEMA
公开(公告)号：EP1012846A4
公开(公告)日：2003-07-09
申请号：EP98929080
申请日：1998-06-12
申请人： MACRONIX INT CO LTD
发明人： LIN YU-SHEN , SHIAU TZENG-HUEI , WAN RAY-LIN
IPC分类号： G11C16/00 , G11C16/10 , G11C16/12 , G11C16/16 , G11C16/34
CPC分类号： G11C16/3413 , G11C16/3404 , G11C16/3409
摘要： A recovery circuit (930) for recovering the control gate and the channel well of a floating gate memory cell to a first recovery potential and a second recovery potential respectively after a program or erase process has been performed on the cell is provided. The floating gate memory cell may include the control gate (80) coupled to a first node (702) at a first program/erase potential, a floating gate (76), the channel well (64) coupled to a second node (704) at a second program/erase potential having a first conductivity type, and drain (88) and source (72) regions within the channel well (64) having a second conductivity type different from the first. The recovery circuit (930) includes control circuitry that provides a recovery control signal indicating when the program or erase process has been completed, and a coupling circuit that connects the control gate (80) to the channel well (64) in response to the recovery control signal.
摘要翻译：提供一种恢复电路，用于在对单元进行编程或擦除处理之后，分别将浮动栅极存储单元的控制栅极和沟道阱恢复到第一恢复电位和第二恢复电位。浮动栅极存储单元可以包括以第一编程/擦除电位耦合到第一节点的控制栅极，浮置栅极，在具有第一导电类型的第二编程/擦除电位下良好耦合到第二节点的沟道，以及漏极以及通道内的源极区具有不同于第一导电类型的第二导电类型。恢复电路包括控制电路，其提供指示编程或擦除过程何时完成的恢复控制信号，以及响应于恢复控制信号将控制门连接到信道的耦合电路。恢复电路还包括当控制栅极和沟道阱电压分别达到第一和第二开关电压时产生第一和第二接地信号的第一和第二电压检测器。第一和第二接地信号被提供给分别响应于接地信号而将控制栅极和沟道良好地偏置到第一和第二恢复电位的第一和第二电压接地电路。在一个实施例中，第一和第二恢复电位连接到地电位的节点，而在另一实施例中，第一导电类型是p型。在另一实施例中，浮动栅极存储单元是三阱阱晶体管，其沟道阱位于集成电路的衬底上的隔离阱内。

10. 发明公开

EP0904589A4 FLOATING GATE MEMORY DEVICE WITH LOW CURRENT PAGE BUFFER 失效
标题翻译：同方BUFFER浮栅存储安排与低功耗
公开(公告)号：EP0904589A4
公开(公告)日：2000-07-12
申请号：EP96921634
申请日：1996-06-14
申请人： MACRONIX INT CO LTD
发明人： HUNG CHUN-HSIUNG , WAN RAY-LIN , LEE YU-SUI
IPC分类号： G11C16/02 , G11C7/10 , G11C11/56 , G11C16/10 , G11C16/34 , G11C16/06
CPC分类号： G11C16/3445 , G11C7/1078 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/10 , G11C16/3436 , G11C16/3459 , G11C2211/5621 , G11C2211/5622 , G11C2211/5642 , G11C2211/5647 , G11C2216/14
摘要： A page mode flash memory or floating gate memory device includes a page buffer (11) based on low current bit latches which enable efficient program, program verify, read and erase verify processes during page mode operation. The array (10) includes bit lines (12) coupled to corresponding columns of cells in the array, and word lines (18) coupled to corresponding rows of cells. A control logic (21) executes the steps of setting a set of bit lines to a precharge voltage level (Vdd or ground), isolating the precharged bit lines, applying a wordline voltage to the wordline of the page of cells to be sensed, and responding to changes in voltage levels of the bit lines to store a constant in the bit latches coupled to the bit lines on which the bit line voltages pass a predetermined threshold. Thus the bit lines of cells, which are in a conductive state during the verify process, discharge without fighting the current required to switch the bit latch.

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