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1. 发明公开

EP0861491A4 METHOD AND SYSTEM FOR SOFT PROGRAMMING ALGORITHM 失效
标题翻译：系统和方法进行软编程算法研究
公开(公告)号：EP0861491A4
公开(公告)日：2001-03-07
申请号：EP95942436
申请日：1995-11-17
申请人： MACRONIX INT CO LTD , YIU TOM DANG HSING
发明人： YIU TOM DANG-HSING , SHONE FUCHIA , LEE I-LONG , CHEN CHIA-SHING , CHEN HUN-SONG , LIU YUAN-CHANG , SHIAU TZENG-HUEI , CHANG KUEN-LONG , WAN RAY-LIN
IPC分类号： G11C16/34 , G11C7/00
CPC分类号： G11C16/3409 , G11C16/3404
摘要： A floating gate memory device which includes control circuits (2, 3, 4) to generate a repair pulse to repair over-erased cells so they may be repaired block-by-block (1). This invention includes repairing the cells by applying a repair pulse to the cell's bit line (10, 11) while maintaining the word line voltage above ground. In a different embodiment, the word line voltage is maintained at two different voltage levels above ground. In the first stage, the word line voltage is maintained between approximately 0.1 volts and 0.2 volts for approximately 100 ms while the repair pulse is applied. In the second stage, the word line voltage is maintained between approximately 0.4 volts and 0.5 volts for approximately 100 ms while the repair pulse is applied.

2. 发明公开

EP1151365A4 RAPID ON CHIP VOLTAGE GENERATION FOR LOW POWER INTEGRATED CIRCUITS 有权
标题翻译： FAST发电机对集成电路的低功率芯片
公开(公告)号：EP1151365A4
公开(公告)日：2002-01-30
申请号：EP98960305
申请日：1998-11-18
申请人： MACRONIX INT CO LTD
发明人： CHANG KUEN-LONG , HUNG CHUN-HSIUNG , CHEN KEN-HUI , HO TIEN-SHIN , LEE I-LONG , SHIAU TZENG-HEI , WAN RAY-LIN
IPC分类号： G11C11/413 , B60K20/00 , C08G59/06 , F02M61/10 , G05F20060101 , G05F1/10 , G05F1/46 , G05F3/02 , G05F3/20 , G11C5/14 , G11C11/407 , G11C16/06 , H01L21/822 , H01L27/02 , H01L27/04
CPC分类号： G05F1/46
摘要： An on chip voltage generation circuit is provided for use on integrated circuits such as flash memory devices with a low power supply voltage. The voltage generation circuit comprises first and second level detectors (209 and 210) and a boost driver (204), wherein the voltage generation circuit pumps charge at first and second rates in response to outputs of the detectors.

3. 发明公开

EP0813751A1 SERIES CAPACITOR CHARGE PUMP 失效
标题翻译：具有串联电容电荷泵
公开(公告)号：EP0813751A1
公开(公告)日：1997-12-29
申请号：EP95914009
申请日：1995-03-09
申请人： MACRONIX INT CO LTD , NIPPON KOKAN KK
发明人： KAMEI TERUHIKO , LEE I-LONG , SOEJIMA KOUTA , WAN RAY-LIN
IPC分类号： G11C16/06 , H01L27/02 , H02M3/07 , H01L29/78
CPC分类号： H01L27/0222 , H02M3/073
摘要： A charge pump apparatus comprises first and second active capacitors (100/101) in series, having a common node (103) between them. The second lead of the second active capacitor (101) is coupled to a particular node (OUT) which drives an output of the charge pump. A pump clock (CLK0) is connected to the first lead of the first active capacitor (100). A voltage clamp (105) is connected to the particular node (OUT) and provides a bias point. A dynamic biasing circuit (108) is connected to the common node (103) and charges the common node (103) and the particular node (OUT) between transitions of the pump clock (CLK0) to keep both active capacitors (100/101) activated during the transitions. The dynamic biasing circuit (108) includes a precharge circuit (63/64) responsive to a charge clock (CLKB) wherein the charge clock (CLKB) has transitions non-overlapping with transitions of the pump clock (CLK0).

4. 发明公开

EP0925586A4 FOWLER-NORDHEIM (F-N) TUNNELING FOR PRE-PROGRAMMING IN A FLOATING GATE MEMORY DEVICE 失效
标题翻译： EERER SCHWEBEGATTERSPEICHERANORDNUNG的FOWLER-NORDHEIM-TUNNELING ZUM VORPROGRAMMIEREN
公开(公告)号：EP0925586A4
公开(公告)日：2000-05-31
申请号：EP97915919
申请日：1997-03-10
申请人： MACRONIX INT CO LTD
发明人： HUNG CHUN HSIUNG , SHIAU TZENG-HUEI , CHENG YAO-WU , LEE I-LONG , SHONE FUCHIA , WAN RAY-LIN
IPC分类号： G11C16/02 , G11C16/04 , G11C16/16 , G11C16/34 , H01L27/115 , G11C16/10
CPC分类号： G11C16/107 , G11C16/0416 , G11C16/16 , G11C16/3454 , G11C16/3459 , H01L27/115
摘要： A new flash memory cell structure comprising a floating gate memory cell is made in a semiconductor substrate (10) having a first conductivity type, such as p-type. A first well (11) within the substrate by having a second conductivity type different from the first conductivity is included. A second well (12) within the first well is also included having the first conductivity type. A drain (14) and a source (13) are formed in the second well having the second conductivity type, and spaced away from one another to define a channel area between the drain (14) and the source (13). A floating gate (15) and a control gate (17) structure is included over the channel area. The floating gate memory cell is coupled with circuits that induce F-N tunneling of electrons out of the floating gate (15) into the channel area of the substrate (10) for erasing by applying a positive voltage to the second well (12), such as a voltage higher than the supply voltage, applying a positive voltage to the first well (11), which is substantially equal to the positive voltage of the second well (12), applying a negative voltage to the control gate (17) of the cell, while the substrate (10) is grounded.
摘要翻译：包括浮动栅极存储单元的新的闪速存储单元结构在具有第一导电类型的半导体衬底（10）中制成，例如p型。包括具有不同于第一导电性的第二导电类型的衬底内的第一阱（11）。第一阱中的第二阱（12）也包括具有第一导电类型。在具有第二导电类型的第二阱中形成漏极（14）和源极（13），并且彼此间隔开以限定漏极（14）和源极（13）之间的沟道区域。在通道区域上包括浮动栅极（15）和控制栅极（17）结构。浮动栅极存储单元与电路耦合，该电路通过向第二阱（12）施加正电压而将电子的FN隧穿从浮动栅极（15）引入到衬底（10）的沟道区域中以进行擦除，例如电压高于电源电压，向第一阱（11）施加正电压，其基本上等于第二阱（12）的正电压，向电池的控制栅极（17）施加负电压而衬底（10）接地。

5. 发明公开

EP0813751A4 SERIES CAPACITOR CHARGE PUMP 失效
标题翻译：具有串联电容电荷泵
公开(公告)号：EP0813751A4
公开(公告)日：1999-03-24
申请号：EP95914009
申请日：1995-03-09
申请人： MACRONIX INT CO LTD , NIPPON KOKAN KK
发明人： KAMEI TERUHIKO , LEE I-LONG , SOEJIMA KOUTA , WAN RAY-LIN
IPC分类号： G11C16/06 , H01L27/02 , H02M3/07 , H01L29/78
CPC分类号： H01L27/0222 , H02M3/073
摘要： A charge pump apparatus comprises first and second active capacitors (100/101) in series, having a common node (103) between them. The second lead of the second active capacitor (101) is coupled to a particular node (OUT) which drives an output of the charge pump. A pump clock (CLK0) is connected to the first lead of the first active capacitor (100). A voltage clamp (105) is connected to the particular node (OUT) and provides a bias point. A dynamic biasing circuit (108) is connected to the common node (103) and charges the common node (103) and the particular node (OUT) between transitions of the pump clock (CLK0) to keep both active capacitors (100/101) activated during the transitions. The dynamic biasing circuit (108) includes a precharge circuit (63/64) responsive to a charge clock (CLKB) wherein the charge clock (CLKB) has transitions non-overlapping with transitions of the pump clock (CLK0).

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