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1. 发明公开

EP1118210A4 METHOD AND APPARATUS FOR PREVENTING KEYSTONE DISTORTION 审中-公开
标题翻译： GERAET UND VERFAHREN ZUR VERMEIDUNG VON TRAPEZOIDALBILDABWEICHUNGEN
公开(公告)号：EP1118210A4
公开(公告)日：2006-08-23
申请号：EP99951673
申请日：1999-10-01
申请人： MACRONIX INT CO LTD
发明人： CHEN CHUN-HUNG , CHEN SHUEI-LIN , TING HOU-CHUN , YANG MENG-SHAN , CHANG TING-YAO , KUO CHUN-HAO
IPC分类号： G03B21/00 , G03B21/14 , G09G3/20 , G09G3/36 , H04N3/233 , H04N5/74 , H04N9/31 , H04N17/00 , H04N3/22 , H04N3/223 , H04N3/227 , H04N3/23 , H04N3/26
CPC分类号： H04N9/3185 , H04N3/2335
摘要： A method and apparatus are provided for preventing keystone distortion in a projected image. A projected image (750a) is produced by projecting light from a light source (102) through a deformed image (700a) rendered on a display device (110) of a projector (100) and onto a viewing surface (130) at a non-perpendicular angle. An original image (700) received for projection is deformed in proportion to the projection angle to generate the deformed image (700a), which is projected to yield the projected image (750a) having proportions closely matching the original image (700). The original image (700) may be resized for storage in memory and/or to fit within a specified area of the display device (110). The apparatus further comprises a digitizer module (206) for receiving the original image (700) and resizing it for storage and a generator module (208) for resizing the image to fit the display device (110). Deformation of the original image (700) may be performed in either or both of digitizer (206) and generator (208).
摘要翻译：一种用于防止梯形失真的方法和装置。通过将显示在显示装置（例如和LCD面板）上的显示图像投射到非垂直和/或水平角的观察表面上来产生投影图像。原始图像与角度成比例地变形以产生显示图像。原始图像也可以被调整大小以存储在存储器中和/或适合于显示设备的指定或可用的区域内。用于防止梯形失真的装置包括数字转换器模块，用于接收和调整原始图像的大小（例如，减小它）以用于存储，并且发生器模块调整（例如，放大）图像以适合显示装置。图像的变形以防止梯形失真可以在数字转换器和发生器中的任一个或两者中对于垂直和水平角度中的任一者或两者执行。

2. 发明公开

EP1185985A4 METHOD AND INTEGRATED CIRCUIT FOR BIT LINE SOFT PROGRAMMING (BLISP) 有权
标题翻译：操作方法及电路进行软编程BITLEITWEGEN
公开(公告)号：EP1185985A4
公开(公告)日：2005-02-02
申请号：EP99931762
申请日：1999-06-08
申请人： MACRONIX INT CO LTD
发明人： SHIAU TZENG-HUEI , WAN RAY-LIN , CHEN HAN SUNG , LIN YU-SHEN , LU WEN-PIN , CHANG TSO-MING
IPC分类号： G11C16/02 , G11C16/06 , G11C16/10 , G11C16/34 , G11C29/00 , G11C29/04 , G11C16/04
CPC分类号： G11C16/3409 , G11C16/10 , G11C16/3404 , G11C16/3445 , G11C29/82 , G11C29/83 , G11C29/832
摘要： A soft program method for an integrated circuit (105), applied to successive subject bit lines and providing efficient convergence of over-erased floating gate memory cells on bit lines, includes a BLISP method. The BLISP method is adapted for low current consumption compared to bulk soft programming method. The soft program is applied to conforming selected bit lines and redundant bit lines which replace defective bit lines. The defective bit lines in first memory array (110) can be disabled during the soft program and replaced by corresponding redundant bit lines disposed in second memory array (170), so that the soft program is not applied to the defective bit lines. By preventing application of the soft program to the defective bit lines, the BLISP method avoids consumption of excessive current that would otherwise be consumed by very low threshold voltage memory cells disposed on the defective bit lines. The excessive current would render the soft program method much less efficient.

3. 发明公开

EP1153393A4 IMPROVED WORD LINE BOOST CIRCUIT 有权
标题翻译：改进后的Power Boost电路FOR字线
公开(公告)号：EP1153393A4
公开(公告)日：2004-06-30
申请号：EP99905656
申请日：1999-02-02
申请人： MACRONIX INT CO LTD
发明人： LIN YU SHEN , HUNG CHUN-HSIUNG , WAN RAY-LIN
IPC分类号： G11C16/06 , G11C5/14 , G11C8/08 , G11C7/00
CPC分类号： G11C5/145 , G11C8/08
摘要： An improved word line boost circuit (100) suitable for use on integrated circuits such as flash memory devices includes a two-step boosting circuit with a floating circuit node. A first circuit (300) provides an initial boost of the output voltage from a precharged voltage. Part of the first circuit is floated, lessening a load on a second circuit. Then, the second circuit (400) provides a second boost of the output voltage with increased power efficiency. A time delay separates the onset of the second boosting operation from the onset of the first boosting operation so as to define a two-step boost.

4. 发明公开

EP0925586A4 FOWLER-NORDHEIM (F-N) TUNNELING FOR PRE-PROGRAMMING IN A FLOATING GATE MEMORY DEVICE 失效
标题翻译： EERER SCHWEBEGATTERSPEICHERANORDNUNG的FOWLER-NORDHEIM-TUNNELING ZUM VORPROGRAMMIEREN
公开(公告)号：EP0925586A4
公开(公告)日：2000-05-31
申请号：EP97915919
申请日：1997-03-10
申请人： MACRONIX INT CO LTD
发明人： HUNG CHUN HSIUNG , SHIAU TZENG-HUEI , CHENG YAO-WU , LEE I-LONG , SHONE FUCHIA , WAN RAY-LIN
IPC分类号： G11C16/02 , G11C16/04 , G11C16/16 , G11C16/34 , H01L27/115 , G11C16/10
CPC分类号： G11C16/107 , G11C16/0416 , G11C16/16 , G11C16/3454 , G11C16/3459 , H01L27/115
摘要： A new flash memory cell structure comprising a floating gate memory cell is made in a semiconductor substrate (10) having a first conductivity type, such as p-type. A first well (11) within the substrate by having a second conductivity type different from the first conductivity is included. A second well (12) within the first well is also included having the first conductivity type. A drain (14) and a source (13) are formed in the second well having the second conductivity type, and spaced away from one another to define a channel area between the drain (14) and the source (13). A floating gate (15) and a control gate (17) structure is included over the channel area. The floating gate memory cell is coupled with circuits that induce F-N tunneling of electrons out of the floating gate (15) into the channel area of the substrate (10) for erasing by applying a positive voltage to the second well (12), such as a voltage higher than the supply voltage, applying a positive voltage to the first well (11), which is substantially equal to the positive voltage of the second well (12), applying a negative voltage to the control gate (17) of the cell, while the substrate (10) is grounded.
摘要翻译：包括浮动栅极存储单元的新的闪速存储单元结构在具有第一导电类型的半导体衬底（10）中制成，例如p型。包括具有不同于第一导电性的第二导电类型的衬底内的第一阱（11）。第一阱中的第二阱（12）也包括具有第一导电类型。在具有第二导电类型的第二阱中形成漏极（14）和源极（13），并且彼此间隔开以限定漏极（14）和源极（13）之间的沟道区域。在通道区域上包括浮动栅极（15）和控制栅极（17）结构。浮动栅极存储单元与电路耦合，该电路通过向第二阱（12）施加正电压而将电子的FN隧穿从浮动栅极（15）引入到衬底（10）的沟道区域中以进行擦除，例如电压高于电源电压，向第一阱（11）施加正电压，其基本上等于第二阱（12）的正电压，向电池的控制栅极（17）施加负电压而衬底（10）接地。

5. 发明公开

EP0931379A4 TRIPLE WELL CHARGE PUMP 失效
标题翻译：三重托盘电荷泵
公开(公告)号：EP0931379A4
公开(公告)日：2000-01-19
申请号：EP96939448
申请日：1996-10-10
申请人： MACRONIX INT CO LTD
发明人： HUNG CHUN-HSIUNG , WAN RAY-LIN , CHENG YAO-WU
IPC分类号： H01L27/02 , H01L29/10 , H02M3/07 , H03K17/56 , H01L29/788 , H03K17/687 , H03K17/74
CPC分类号： H01L27/0222 , H01L29/1087 , H02M3/073
摘要： An improved charge pump design. This charge pump comprises at least one pumping transistor having a triple well arrangement (206, 204, 206). This triple well pump transistor has a source and a drain (210, 212) of a first conductive type formed on a first well (206) having an opposite conductive type. A second well (204) having the first conductive type is formed outside of the first well (206). The source region, first well and second well are set to substantially the same potential. One aspect of this configuration is that the first well forms a semiconductor diode with the drain region (212). Another aspect of this arrangement is that the body effect of the transistor is reduced. The reduction in body effect reduces the threshold voltage of the transistor. It is found that the above mentioned diode and threshold voltage of the tansistor, singly and in combination, allow the charge pump to operate more efficiently.

6. 发明公开

EP0813751A4 SERIES CAPACITOR CHARGE PUMP 失效
标题翻译：具有串联电容电荷泵
公开(公告)号：EP0813751A4
公开(公告)日：1999-03-24
申请号：EP95914009
申请日：1995-03-09
申请人： MACRONIX INT CO LTD , NIPPON KOKAN KK
发明人： KAMEI TERUHIKO , LEE I-LONG , SOEJIMA KOUTA , WAN RAY-LIN
IPC分类号： G11C16/06 , H01L27/02 , H02M3/07 , H01L29/78
CPC分类号： H01L27/0222 , H02M3/073
摘要： A charge pump apparatus comprises first and second active capacitors (100/101) in series, having a common node (103) between them. The second lead of the second active capacitor (101) is coupled to a particular node (OUT) which drives an output of the charge pump. A pump clock (CLK0) is connected to the first lead of the first active capacitor (100). A voltage clamp (105) is connected to the particular node (OUT) and provides a bias point. A dynamic biasing circuit (108) is connected to the common node (103) and charges the common node (103) and the particular node (OUT) between transitions of the pump clock (CLK0) to keep both active capacitors (100/101) activated during the transitions. The dynamic biasing circuit (108) includes a precharge circuit (63/64) responsive to a charge clock (CLKB) wherein the charge clock (CLKB) has transitions non-overlapping with transitions of the pump clock (CLK0).

7. 发明公开

EP0829086A4 TECHNIQUE FOR RECONFIGURING A HIGH DENSITY MEMORY 失效
标题翻译： TECHNIK ZUM REKONFIGURIEREN EINES SPEICHERS HOHER DICHTE
公开(公告)号：EP0829086A4
公开(公告)日：1998-12-02
申请号：EP95923687
申请日：1995-05-31
申请人： MACRONIX INT CO LTD
发明人： LIOU KONG-MOU , YIU TOM DANG-HSING , WAN RAY-LIN , CHENG YAO-WU , HUNG CHUN-HSIUNG , LIN TIEN-LER , HU TING-CHUNG
IPC分类号： G11C16/06 , G11C8/08 , G11C8/10 , G11C8/12 , G11C16/08 , G11C29/00 , G11C29/04 , G11C7/00
CPC分类号： G11C29/76 , G11C8/08 , G11C8/10 , G11C8/12 , G11C16/08
摘要： A flexible technique for improving yield of manufacturing of high density of memory devices, such as flash EEPROM, involves reconfiguring an integrated memory array having a plurality of sectors (10) selected by an address decoder (11, 13) in response to an N bit field in an address (17). If defective sectors are detected in the array, it is partitioned to disable defective sectors by configuring a sector decoder (12) to prevent access to the defective sectors while maintaining sequential addressing remaining in the array. The step of partitioning includes configuring the sector decoder (12) to replace a defective sector in one half of the array by another sector in the other half of the array having N-m of the address bits in common with the defective sector when m is between 1 and N-1.
摘要翻译：用于提高诸如快速EEPROM之类的高密度存储器件的制造产率的灵活技术涉及响应于N位而重新配置具有由地址解码器（11,13）选择的多个扇区（10）的集成存储器阵列字段在地址（17）中。如果在阵列中检测到有缺陷的扇区，则通过配置扇区解码器（12）来禁止有缺陷的扇区，以防止访问有缺陷的扇区，同时保持阵列中的顺序寻址。划分步骤包括配置扇区解码器（12），以便在阵列的另一半中的阵列的另一半中的另一个扇区替换阵列的一半中的缺陷扇区，当m在1之间时，该阵列具有与缺陷扇区相同的Nm个地址位和N-1。

8. 发明公开

EP0714546A4 ERASE AND PROGRAM VERIFICATION CIRCUIT FOR NON-VOLATILE MEMORY 有权转让
标题翻译：擦除和编程验证电路用于非易失性存储器
公开(公告)号：EP0714546A4
公开(公告)日：1998-04-08
申请号：EP93914257
申请日：1993-05-28
申请人： MACRONIX INT CO LTD
发明人： LIN TIEN-LER , YIU TOM DANG-HSING , CHAO LIANG
IPC分类号： G11C17/00 , G11C16/02 , G11C16/04 , G11C16/06 , G11C16/28 , G11C16/34 , G11C29/50 , G11C16/00
CPC分类号： G11C16/3445 , G06F2201/81 , G11C16/04 , G11C16/0491 , G11C16/28 , G11C16/3436 , G11C16/3459 , G11C29/028 , G11C29/50 , G11C2029/5004
摘要： For non-volatile memory devices, such as flash EPROM integrated circuits, which have memory cells (10) and reference cells (23), and sense circuitry (27) responsive to addressed memory cells (10) and the reference cells (23), and in which a read potential is supplied to the gate of the selected memory cells and a reference potential is supplied to the gate of a reference memory cell during a read mode, the state of the programmable memory cells (10) is verified by (1) supplying a first verify potential to the gate of an address programmable memory cell; and (2) supplying a second verify potential to the gate of the reference cell which is different from the first verify potential. Because cell current is a very strong function of the gate voltage, applying different gate voltages to the memory (10) and reference cells (23) is equivalent to adjusting the sense ratio.

9. 发明公开

EP0702833A4 FAST FLASH EPROM PROGRAMMING AND PRE-PROGRAMMING CIRCUIT DESIGN 有权转让
标题翻译： SCHNELLER FLASH-EPROM-PROGRAMMIERUNGS- UND VORPROGRAMMIERUNGSSCHALTUNGSENTWURF
公开(公告)号：EP0702833A4
公开(公告)日：1997-08-13
申请号：EP93916409
申请日：1993-05-28
申请人： MACRONIX INT CO LTD
发明人： YIU TOM DANG-HSING , WAN RAY L , HSIAO LING-WEN NO , LIN TIEN-LER , SHONE FUCHIA F
IPC分类号： G11C17/00 , G11C16/02 , G11C16/04 , G11C16/06 , G11C16/12 , G11C16/16 , G11C16/24 , G11C16/30 , G11C16/00
CPC分类号： G11C16/30 , G11C16/12 , G11C16/16 , G11C16/24
摘要： A circuit (10) for speeding up the pre-programming of floating gate storage transistors such as FLASH EPROMS, and particularly speeding up the pre-programming of a block or array (11) of floating gate storage transistors includes a controllable voltage source (18) that supplies gate programming potential across the control gate and source of the FLASH EPROM transistor cells to be programmed. A control circuit is provided that controls the voltage source to vary the gate programming potential during a programming interval as a function of time in order to decrease the time required for a given amount of charge movement to program the selected floating gate transistors. The wordline voltages are varied, while the source voltage is held constant.
摘要翻译：用于加速诸如FLASH EPROMS之类的浮置栅极存储晶体管的预编程并且特别是加速浮置栅极存储晶体管的模块或阵列（11）的预编程的电路（10）包括可控电压源（18 ），它提供跨控制栅极和要编程的FLASH EPROM晶体管单元的源极的栅极编程电位。提供控制电路，其控制电压源以在编程间隔期间改变栅极编程电位作为时间的函数，以便减少给定量的电荷移动以编程所选择的浮置栅极晶体管所需的时间。字线电压是变化的，而电源电压保持不变。

10. 发明公开

EP1058930A4 A MEMORY SUPPORTING MULTIPLE ADDRESS PROTOCOLS 失效
标题翻译：对记忆支持多种地址协议
公开(公告)号：EP1058930A4
公开(公告)日：2005-02-16
申请号：EP98901220
申请日：1998-01-06
申请人： MACRONIX INT CO LTD
发明人： CHEN HAN SUNG , SHIAU TZENG-HUEI , CHANG TSO-MING , WAN RAY-LIN , SHONE FUCHIA
IPC分类号： G11C16/06 , G06F9/445 , G06F12/00 , G06F12/02 , G11C8/00 , G11C16/08 , G11C16/10
CPC分类号： G06F9/4403 , G11C8/00 , G11C16/08 , G11C16/10
摘要： The present invention provides a new memory device for storage of boot code for microprocessors. The device includes a memory array (130), a first block, and decoders (118, 120). The first block is defined as rows of the memory array. The decoders decode a memory access request for the data. The memory access request may be either one of a top-down or bottom-up address protocol. In another embodiment, an integrated circuit memory includes: a memory array (130), a decoder, a control (136), and a logic gate (132). The decoders select a row of the memory array. The control outputs either a bottom-up or a top-down address protocol signal. The logic gate outputs a logical 'Exclusive Or' of the control signal and a corresponding bit of the memory request, whereby a memory request in a bottom-up address protocol is converted to a memory address in a top-down address protocol.

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