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1. 发明授权

EP1665286B1 INTEGRATED CIRCUIT AND A METHOD OF CACHE REMAPPING 失效转让
标题翻译：集成电路和高速缓冲存储器的一种方法
公开(公告)号：EP1665286B1
公开(公告)日：2007-07-11
申请号：EP04769812.1
申请日：2004-08-17
申请人： Koninklijke Philips Electronics N.V.
发明人： BINK, Adrianus, J. , STRAVERS, Paul
IPC分类号： G11C29/00 , G06F12/08 , G06F12/10 , G06F11/14
CPC分类号： G11C29/76 , G06F12/0846 , G06F12/0864 , G11C29/88
摘要： An integrated circuit is provided with at least one processing unit (TM), a cache memory (L2 BANK) having a plurality of memory modules, and remapping means (RM) for performing an unrestricted remapping within said plurality of memory modules. Accordingly, faulty modules can be remapped without limitations in order to optimise the utilization of the memory modules by providing an even distribution of the faulty modules.
摘要翻译：集成电路具有至少一个处理单元（TM），具有多个存储器模块的高速缓冲存储器（L2BANK）以及用于在所述多个存储器模块内执行无限制重映射的重映射装置（RM）。因此，可以无限制地重新映射故障模块，以便通过提供故障模块的均匀分布来优化存储器模块的利用率。

2. 发明公开

EP1728083A2 ELECTRONIC CIRCUIT 审中-公开
标题翻译：电子电路
公开(公告)号：EP1728083A2
公开(公告)日：2006-12-06
申请号：EP05703033.0
申请日：2005-02-24
申请人： Koninklijke Philips Electronics N.V.
发明人： BINK, Adrianus, J. , DE CLERCQ, Mark, N., O.
IPC分类号： G01R31/28
CPC分类号： G06F11/2236 , G01R31/31723 , G01R31/318541
摘要： An electronic circuit is provided that comprises first and second combinational logic blocks and a latch positioned between the combinational logic blocks; wherein the electronic circuit is adapted to operate in a normal mode in which the latch is opened and closed in response to an enable signal, and a test mode in which the latch is held open.

3. 发明公开

EP1379941A1 EMULATION COPROCESSOR WITH BRANCH MECHANISM 审中-公开
标题翻译：具有分支机制的仿真协处理器
公开(公告)号：EP1379941A1
公开(公告)日：2004-01-14
申请号：EP02713159.8
申请日：2002-04-02
申请人： Koninklijke Philips Electronics N.V.
发明人： BINK, Adrianus, J. , AUGUSTEIJN, Alexander , HOOGENDIJK, Paul, F. , VAN DE WIEL, Hendrikus, W. J.,Inter. Octroi. B.V.
IPC分类号： G06F9/318 , G06F9/32
CPC分类号： G06F9/30174 , G06F9/321 , G06F9/322 , G06F9/3879
摘要： The problem of mis-match between a program counter (14) of a CPU (10) and a byte code counter (18) of an instruction path coprocessor (IPC) (16) is addressed by causing the IPC (16) to translate IPC branch instructions to the CPU branch instructions, in which the CPU branch instructions implicitly indicate whether a corresponding IPC branch instructions should be taken and in which the CPU branch instruction will cause the CPU (10) to set its own program counter (14) to a safe location in the IPC range to avoid overflow.
摘要翻译：通过使IPC（16）翻译IPC（10）来寻址CPU（10）的程序计数器（14）与指令路径协处理器（IPC）（16）的字节码计数器（18）之间的不匹配问题分支指令提供给CPU分支指令，其中CPU分支指令隐含地指示是否应该采取对应的IPC分支指令，并且其中CPU分支指令将使得CPU（10）将其自己的程序计数器（14）设置为安全的位置在IPC范围内以避免溢出。

4. 发明公开

EP2052330A2 ELECTRONIC DEVICE AND METHOD FOR SYNCHRONIZING A COMMUNICATION 审中-公开
标题翻译：电子设备和方法用于同步通信
公开(公告)号：EP2052330A2
公开(公告)日：2009-04-29
申请号：EP07805313.9
申请日：2007-08-06
申请人： Koninklijke Philips Electronics N.V.
发明人： TIMMERMANS, Daniel , VAN BERKEL, Cornelis, H. , BINK, Adrianus, J.
IPC分类号： G06F15/78
CPC分类号： H04L49/40 , G06F15/7825 , H04L45/00 , H04L45/60 , H04L49/109 , H04L49/1546 , Y02D10/12 , Y02D10/13
摘要： An electronic device is provided which comprises a plurality of processing units (IP1-IP6) and a flit-synchronous network-based interconnect (N) for coupling the processing units (IP1-IP6). The network-based interconnect (N) comprises at least one first and at least one second link. The at least one second link comprises N pipeline stages. The communication via the at least one second link and the N pipeline stages constitutes a word-asynchronous communication.

5. 发明公开

EP1728152A2 PIPELINE CIRCUIT 有权
标题翻译：流水线电路
公开(公告)号：EP1728152A2
公开(公告)日：2006-12-06
申请号：EP05708837.9
申请日：2005-02-24
申请人： Koninklijke Philips Electronics N.V.
发明人： BINK, Adrianus, J. , DE CLERCQ, Mark, N., O.
IPC分类号： G06F9/38
CPC分类号： G06F9/3871 , G06F1/3203 , G06F21/755
摘要： There is provided an electronic circuit that is harder to crack using power analysis techniques, the electronic circuit comprising first and second pipeline stages and a latch positioned between the pipeline stages; wherein the electronic circuit is adapted to operate in a normal mode in which the latch is opened and closed in response to an enable signal, and a reduced mode in which the latch is held open to reduce a current peak associated with the opening and closing of the latch.

6. 发明公开

EP1358550A1 SYNCHRONIZATION OF A MAIN PROCESSOR WITH AN INSTRUCTION PATH COPROCESSOR 审中-公开
标题翻译： SYNCHRONIZING主处理器使用命令协处理器A链
公开(公告)号：EP1358550A1
公开(公告)日：2003-11-05
申请号：EP02737620.1
申请日：2002-01-04
申请人： Koninklijke Philips Electronics N.V.
发明人： BINK, Adrianus, J. , AUGUSTEIJN, Alexander , HOOGENDIJK, Paul, F. , VAN DE WIEL, Hendrikus, W., J. , YEDEMA, Wim, F., D.
IPC分类号： G06F9/318 , G06F9/38
CPC分类号： G06F9/3877 , G06F9/30174 , G06F9/3802
摘要： An instruction path coprocessor (IPC) (16) observes the value of a CPU program counter (14) of a CPU (10) to detect whether the IPC (16) should be active. The IPC (16) uses the value of the CPU program counter also to determine how the IPC should update its own IPC program counter. When a function is called, an exception or interrupt is handled or a jump to a target specified in a register is executed, an address is prepared that, when loaded into the CPU program counter, will cause the IPC to update its IPC program counter as required for the return from function call, exception or interrupt or jump. The prepared address is loaded into the CPU (10) program counter. The program counter (14) return address, for example, contains the virtual machine return address and a bit set to indicate that the address should be treated as a return from the jump to sub-routine.

7. 发明授权

EP1368732B1 DIGITAL SIGNAL PROCESSING APPARATUS 有权
标题翻译：数字信号处理器设备
公开(公告)号：EP1368732B1
公开(公告)日：2008-01-23
申请号：EP01983541.2
申请日：2001-10-10
申请人： Koninklijke Philips Electronics N.V.
发明人： LEIJTEN, Jeroen, A., J. , BEKOOIJ, Marco, J., G. , BINK, Adrianus, J. , VAN GAGELDONK, Johan, S., H. , HOOGERBRUGGE, Jan , MESMAN, Bart
IPC分类号： G06F9/30
CPC分类号： G06F9/30116 , G06F9/30123 , G06F9/30149 , G06F9/30181 , G06F9/3836 , G06F9/3859 , G06F9/3861 , G06F9/461 , G06F9/50
摘要： The present invention relates to a digital signal processing apparatus comprising a plurality of available hardware resource means and a first instruction set means having access to said available hardware resource means, so that at least a part of said hardware resource means execute operations under control of said first instruction set means, and further comprising a second instruction set means having access to only a predetermined limited subset of said plurality of available hardware resource means, so that at least a part of said predetermined limited subset of said hardware resource means execute operations under control of said second instruction set means. Further, the present invention relates to a method for processing digital signals in a digital signal processing apparatus comprising a plurality of available hardware resource means, wherein at least a part of said hardware resource means execute operations under control of a first instruction set, and wherein at least a part of a predetermined limited subset of said plurality of available hardware resource means execute operations under control of a second instruction set having access to only said predetermined limited subset of said hardware resource means.

8. 发明公开

EP1745367A2 PIPELINED ASYNCHRONOUS INSTRUCTION PROCESSOR CIRCUIT 有权转让
标题翻译：管道异步指令处理器电路
公开(公告)号：EP1745367A2
公开(公告)日：2007-01-24
申请号：EP05732298.4
申请日：2005-04-21
申请人： Koninklijke Philips Electronics N.V.
发明人： BINK, Adrianus, J. , DE CLERCQ, Mark, N., O.
IPC分类号： G06F9/38
CPC分类号： G06F9/3824 , G06F9/3855 , G06F9/3871
摘要： A data processing circuit contains a register file (17) with a write port and a pipeline of instruction processing stages (10a-d). A timing circuit (14) is arranged to time transfer of instruction dependent information between the stages at mutually different time points, so that processing of successive instructions in respective stages partially overlaps. A first and a second one of the stages (10c, d) are in series in the pipeline. Each of the first and a second one of the stages has a result output for writing a result to the write port, if instruction dependent information in the stage concerned (10c, d) requires writing. A write sequencing circuit (144) performs write tests alternately for instruction dependent information in the first and second one of the stages (10c, d). When the write sequencing circuit (144) performs the write test for a particular one of the stages (10c, d), it tests whether the instruction dependent information in the particular one of the stages (10c, d) requires writing of a result. If so, the write sequencing circuit (144), delays transfer of new instruction dependent information through the pipeline (10a-d) to the particular one of the stages (10c,d) until the write port has been committed to writing the result before any results that the write port is subsequently committed to write.

9. 发明公开

EP1346282A1 SIGNAL PROCESSING DEVICE AND METHOD FOR SUPPLYING A SIGNAL PROCESSING RESULT TO A PLURALITY OF REGISTERS 审中-公开
标题翻译：信号处理装置和方法喂养的信号处理结果多寄存器
公开(公告)号：EP1346282A1
公开(公告)日：2003-09-24
申请号：EP01991757.4
申请日：2001-11-23
申请人： Koninklijke Philips Electronics N.V.
发明人： LEIJTEN, Jeroen, A., J. , BEKOOIJ, Marco, J., G. , BINK, Adrianus, J. , VAN GAGELDONK, Johan, S., H. , HOOGERBRUGGE, Jan , MESMAN, Bart , VAN EIJK, Cornelis, A., J.
IPC分类号： G06F9/38 , G06F9/30
CPC分类号： G06F9/3012 , G06F9/30098 , G06F9/3885
摘要： The present invention relates to a signal processing device and method of supplying a signal processing result to a plurality of registers arranged in different register files, wherein a plurality of different register files are selected based on a corresponding indication in said instruction word, and the register address is supplied to said selected register files. Thereby, result values can be broadcasted to multiple registers in a single processor cycle, while a copy operation between different register files is eliminated. Broadcasting is thus implemented via overlapping register address spaces, since physical registers having the same logical register address are provided in different register files.

10. 发明公开

EP1073951A1 DATA PROCESSOR WITH A CONFIGURABLE FUNCTIONAL UNIT AND METHOD USING SUCH A DATA PROCESSOR 审中-公开
标题翻译：与地图对机组及申请程序数据处理器
公开(公告)号：EP1073951A1
公开(公告)日：2001-02-07
申请号：EP00903638.5
申请日：2000-01-26
申请人： Koninklijke Philips Electronics N.V.
发明人： DE OLIVEIRA KASTRUP PEREIRA, Bernardo , BINK, Adrianus, J. , HOOGERBRUGGE, Jan
IPC分类号： G06F9/318
CPC分类号： G06F9/30181 , G06F9/3885 , G06F9/3897 , G06F15/7867
摘要： A processor contains a configurable functional unit that is capable of executing reconfigurable instructions, whose effect can be redefined at run-time by loading a configuration program. Reconfigurable instructions are selected in combinations of more than one different reconfigurable instruction. A respective configuration program for each combination of instructions is generated. Each time when an instruction from one of the combinations is needed during execution and the configurable functional unit is not configured with the configuration program for that combination, the configuration program for all of the instructions of that combination is loaded into the configurable functional unit. The reconfigurable instructions selects which instruction of the combination is executed.

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