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1. 发明授权

EP0405220B1 Semiconductor memory device 失效
标题翻译：一种半导体存储器件
公开(公告)号：EP0405220B1
公开(公告)日：1996-08-14
申请号：EP90111092.4
申请日：1990-06-12
申请人： KABUSHIKI KAISHA TOSHIBA , TOSHIBA MICRO-ELECTRONICS CORPORATION
发明人： Iwahashi, Hiroshi
IPC分类号： G11C7/00 , G11C16/06
CPC分类号： G11C7/14 , G11C16/28

2. 发明公开

EP0622807A2 Semiconductor memory device 失效
标题翻译： Halbleiterspeicheranordnung。
公开(公告)号：EP0622807A2
公开(公告)日：1994-11-02
申请号：EP94106689.6
申请日：1994-04-28
申请人： KABUSHIKI KAISHA TOSHIBA , TOSHIBA MICRO-ELECTRONICS CORPORATION
发明人： Iwahashi, Hiroshi
IPC分类号： G11C16/06
CPC分类号： G11C8/10 , G11C16/08
摘要： A semiconductor memory device, comprising: first row lines (WL10); selecting transistors (4) driven by the first row lines (WL10); second row lines (WL11-WL14); memory cells (31-34) driven by the second row lines (WL11-WL14) and connected in series with the selecting transistors (4); first selecting means (Figs. 4, 6, 8 and 14) for selecting the first row lines (WL10); second selecting means (Figs. 5 and 7) for selecting the second row lines (WL11-WL14); column lines (128) connected to the selecting transistors (4); data detecting means (SA) connected to the column lines (128), for detecting data stored in the memory cells (M11-M14); first switching means (51-54, 61-64) connected between the first selecting means (Figs. 4, 6, 8 and 14) and the second row lines (WL11-WL14), for selecting the second row lines (WL11-WL14) in response to the second selecting means (Figs. 5 and 7); and second switching means (21-24) connected between a potential supply terminal (VA) for supplying a predetermined potential and the second row lines (WL11-WL14), for selecting the second row lines (WL11-WL14) in response to the second selecting means.
摘要翻译：一种半导体存储器件，包括：第一行线（WL10）; 选择由第一行线驱动的晶体管（4）; 第二行线（WL11-WL14）; 由第二行线（WL11-WL14）驱动并与选择晶体管（4）串联连接的存储单元（31-34）; 用于选择第一行线（WL10）的第一选择装置（图4,6,8和14）。用于选择第二行线（WL11-WL14）的第二选择装置（图5和图7）; 连接到选择晶体管（4）的列线（128）; 连接到列线（128）的数据检测装置（SA），用于检测存储在存储单元（M11-M14）中的数据; 连接在第一选择装置（图4,6,8和14）与第二行线（WL11-WL14）之间的第一开关装置（51-54,61-64）用于选择第二行线（WL11-WL14 ）响应于第二选择装置（图5和7）; 以及连接在用于提供预定电位的电位供给端子（VA）和第二行线（WL11-WL14）之间的第二开关装置（21-24），用于响应于第二行线选择第二行线（WL11-WL14）选择装置（图5和图7）。

3. 发明公开

EP0410473A2 Semiconductor integrated circuit 失效
标题翻译：半导体集成电路
公开(公告)号：EP0410473A2
公开(公告)日：1991-01-30
申请号：EP90114459.2
申请日：1990-07-27
申请人： KABUSHIKI KAISHA TOSHIBA , TOSHIBA MICRO-ELECTRONICS CORPORATION
发明人： Kato, Hideo , Kikuchi, Shinichi , Nakai, Hiroto , Iwahashi, Hiroshi
IPC分类号： H03K19/003
CPC分类号： H03K19/00384 , H03K19/00361
摘要： There is disclosed a semiconductor integrated circuit provided with an input circuit including an N-channel MOS transistor (N2) of which threshold voltage is set to a value lower than those of N-channel MOS transistors (N1, N3, N4) constituting other internal circuits of the integrated circuit. Thus, a circuit having a high operating margin for power supply noises is provided. This circuit further comprises a P-channel MOS transistor (P2) constituting a portion of a NOR gate or a NAND gate together with the above-mentioned N-channel MOS transistor (N2).
摘要翻译：公开了一种设置有输入电路的半导体集成电路，该输入电路包括阈值电压被设置为低于构成其他内部N沟道MOS晶体管（N1，N3，N4）的值的N沟道MOS晶体管（N2）集成电路的电路。因此，提供了具有用于电源噪声的高运行容限的电路。该电路还包括与上述N沟道MOS晶体管（N2）一起构成NOR门或NAND门的一部分的P沟道MOS晶体管（P2）。

4. 发明授权

EP0639860B1 Non-volatile semiconductor memory 失效
标题翻译：的非易失性半导体存储器
公开(公告)号：EP0639860B1
公开(公告)日：2000-06-28
申请号：EP94115451.0
申请日：1989-09-14
申请人： KABUSHIKI KAISHA TOSHIBA , TOSHIBA MICRO-ELECTRONICS CORPORATION
发明人： Asano, Masamichi , Iwahashi, Hiroshi , Kirisawa, Ryouhei , Nakayama, Ryozo , Inoue, Satoshi , Shirota, Riichiro , Endoh, Tetsuo , Masuoka, Fujio
IPC分类号： H01L27/115 , H01L29/788
CPC分类号： H01L27/11519 , G11C16/0483 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L29/7883 , H01L29/7885

5. 发明公开

EP0640982A3 Non-volatile semiconductor memory device and data programming method 失效
标题翻译： NichtflüchtigeHalbleiterspeicheranordnung和Datenprogrammierverfahren。
公开(公告)号：EP0640982A3
公开(公告)日：1997-10-15
申请号：EP94113374.6
申请日：1994-08-26
申请人： KABUSHIKI KAISHA TOSHIBA , TOSHIBA MICRO-ELECTRONICS CORPORATION
发明人： Iwahashi, Hiroshi
IPC分类号： G11C16/06 , G11C16/04
CPC分类号： G11C16/12 , G11C16/0483
摘要： In a non-volatile semiconductor memory, a large current can be flowed through the memory cell during reading. The number of the column lines can be reduced. The electron injection to the floating gates of the respective memory cells is averaged to reduce the dispersion of the threshold voltages thereof. The electron emission from the floating gates of the respective memory cells is also averaged to reduce the dispersion of the threshold voltages thereof. An increase in chip size due to latch circuits can be prevented. In a given memory cell block, or bundle a negative threshold voltage is allocated to the cells corresponding to which ever logic state ("1" or "0") occurs most in that block. A single column line is used in common for two adjacent memory blocks. To inject electrons to the floating gates of the memory cells, voltage is increased gradually and stopped when electrons have been injected up to a predetermined injection rate. Electrons are once emitted from the floating gates, and thereafter the electrons are injected again to store one of a binary data. Further, the data latch circuits can be formed at any positions remote from the memory cell array.
摘要翻译：在非易失性半导体存储器中，在读取期间可以通过存储单元流过大电流。可以减少列线的数量。对各个存储单元的浮置栅极的电子注入被平均以减小其阈值电压的偏差。来自相应存储单元的浮置栅极的电子发射也被平均以减小其阈值电压的偏差。可以防止由于锁存电路引起的芯片尺寸的增加。通过注意到二进制数据的多个“0”或“1”中的任何一个存储在存储器单元组或块的存储单元中，负阈值电压被分配给用于存储更多位侧的存储单元二进制数据的数据。对于两个相邻的存储器块，共同使用单列线。为了将电子注入到存储单元的浮动栅极，电压逐渐增加并且当电子注入到预定的注入速率时停止。电子一次从浮置栅极发射，此后再次注入电子以存储二进制数据之一。此外，数据锁存电路可以形成在远离存储单元阵列的任何位置处。

6. 发明授权

EP0410473B1 Semiconductor integrated circuit 失效
公开(公告)号：EP0410473B1
公开(公告)日：1995-11-15
申请号：EP90114459.2
申请日：1990-07-27
申请人： KABUSHIKI KAISHA TOSHIBA , TOSHIBA MICRO-ELECTRONICS CORPORATION
发明人： Kato, Hideo , Kikuchi, Shinichi , Nakai, Hiroto , Iwahashi, Hiroshi
IPC分类号： H03K19/003
CPC分类号： H03K19/00384 , H03K19/00361

7. 发明公开

EP0405220A3 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：EP0405220A3
公开(公告)日：1994-02-23
申请号：EP90111092.4
申请日：1990-06-12
申请人： KABUSHIKI KAISHA TOSHIBA , TOSHIBA MICRO-ELECTRONICS CORPORATION
发明人： Iwahashi, Hiroshi
IPC分类号： G11C7/00 , G11C16/06
CPC分类号： G11C7/14 , G11C16/28
摘要： A semiconductor memory device is constituted a memory cell for storing a binary data, a first reference cell (DC11,....DCm1), storing a first logic level of a binary data, a second reference cell (DC12,....DCm2) storing a second logic level of a binary data, a first load circuit (13) connected to the memory cell, a second load circuit (14) connected to the first reference cell, a third load circuit (24) connected to the second reference cell and a data detection circuit (25) for detecting the stored data of the memory cell by comparing an output from the first load circuit (13) with the outputs from the second and third load circuits (14,24).
摘要翻译：一种半导体存储器件包括用于存储二进制数据的存储器单元，存储二进制数据的第一逻辑电平的第一参考单元（DC11，... DCm1），第二参考单元（DC12，...， DCm2），存储二进制数据的第二逻辑电平，连接到存储单元的第一负载电路（13），连接到第一参考单元的第二负载电路（14），连接到第二负载电路参考单元和数据检测电路（25），用于通过比较来自第一负载电路（13）的输出与来自第二和第三负载电路（14,24）的输出来检测存储单元的存储数据。

8. 发明公开

EP0410473A3 Semiconductor integrated circuit 失效
公开(公告)号：EP0410473A3
公开(公告)日：1991-07-31
申请号：EP90114459.2
申请日：1990-07-27
申请人： KABUSHIKI KAISHA TOSHIBA , TOSHIBA MICRO-ELECTRONICS CORPORATION
发明人： Kato, Hideo , Kikuchi, Shinichi , Nakai, Hiroto , Iwahashi, Hiroshi
IPC分类号： H03K19/003
CPC分类号： H03K19/00384 , H03K19/00361
摘要： There is disclosed a semiconductor integrated circuit provided with an input circuit including an N-channel MOS transistor (N2) of which threshold voltage is set to a value lower than those of N-channel MOS transistors (N1, N3, N4) constituting other internal circuits of the integrated circuit. Thus, a circuit having a high operating margin for power supply noises is provided. This circuit further comprises a P-channel MOS transistor (P2) constituting a portion of a NOR gate or a NAND gate together with the above-mentioned N-channel MOS transistor (N2).

9. 发明公开

EP0640982A2 Non-volatile semiconductor memory device and data programming method 失效
标题翻译：的非易失性半导体存储装置和数据编程方法。
公开(公告)号：EP0640982A2
公开(公告)日：1995-03-01
申请号：EP94113374.6
申请日：1994-08-26
申请人： KABUSHIKI KAISHA TOSHIBA , TOSHIBA MICRO-ELECTRONICS CORPORATION
发明人： Iwahashi, Hiroshi
IPC分类号： G11C16/06 , G11C16/04
CPC分类号： G11C16/12 , G11C16/0483
摘要： In a non-volatile semiconductor memory, a large current can be flowed through the memory cell during reading. The number of the column lines can be reduced. The electron injection to the floating gates of the respective memory cells is averaged to reduce the dispersion of the threshold voltages thereof. The electron emission from the floating gates of the respective memory cells is also averaged to reduce the dispersion of the threshold voltages thereof. An increase in chip size due to latch circuits can be prevented.
In a given memory cell block, or bundle a negative threshold voltage is allocated to the cells corresponding to which ever logic state ("1" or "0") occurs most in that block. A single column line is used in common for two adjacent memory blocks.
To inject electrons to the floating gates of the memory cells, voltage is increased gradually and stopped when electrons have been injected up to a predetermined injection rate. Electrons are once emitted from the floating gates, and thereafter the electrons are injected again to store one of a binary data. Further, the data latch circuits can be formed at any positions remote from the memory cell array.

10. 发明公开

EP0347935A3 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：EP0347935A3
公开(公告)日：1991-05-29
申请号：EP89111475.3
申请日：1989-06-23
申请人： KABUSHIKI KAISHA TOSHIBA , TOSHIBA MICRO-ELECTRONICS CORPORATION
发明人： Nakai, Hiroto , Iwahashi, Hiroshi , Kanazawa, Kazuhiha , Kumagai, Shigeru , Sato, Isao
IPC分类号： G11C16/06 , G11C7/06
CPC分类号： G11C7/12 , G11C7/062 , G11C7/14 , G11C16/28
摘要： In a semiconductor memory device, a first load circuit (14A) is coupled with the column lines (BL1,..., BLn). first dummy cells (DC1,..., DCm) are connected to a dummy column line (DBL), a second load circuit (14B) is connected to the dummy column line, a second dummy cell (DCm+1) is connected to the dummy column line, and a sense amplifier (15) senses the data stored in the memory cell in accordance with a potential difference between the column line and the dummy column line. In semiconductor memory devices thus arranged, the second dummy cell is set in an on state normally. The connection of the second dummy cell with the dummy line changes a current flowing to the dummy line at the time of row line switching, thereby to hold back a rise of the reference potential at the time of the row line switching.
摘要翻译：在半导体存储器件中，第一负载电路（14A）与列线（BL1，...，BLn）耦合。第一虚拟单元（DC1，...，DCm）连接到虚拟列线（DBL），第二负载电路（14B）连接到虚拟列线，第二虚拟单元（DCm + 1）连接到虚拟列线虚拟列线和读出放大器（15）根据列线和虚拟列线之间的电位差来读出存储在存储单元中的数据。在这样配置的半导体存储器件中，第二虚设单元通常处于导通状态。第二虚拟单元与虚拟线的连接在行线切换时改变流向虚拟线的电流，从而抑制行线切换时的参考电位的上升。

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