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1. 发明授权

EP0774781B1 Method of forming studs within an insulating layer on a semiconductor wafer 失效
标题翻译：在绝缘层中载体的制造方法，在半导体晶片上
公开(公告)号：EP0774781B1
公开(公告)日：2007-01-03
申请号：EP96308103.9
申请日：1996-11-08
申请人： International Business Machines Corporation
发明人： Gambino, Jeffrey Peter , Jaso, Mark Anthony , Nesbit, Larry Alan
IPC分类号： H01L21/768 , H01L21/285
CPC分类号： H01L21/3212 , H01L21/76819 , H01L21/7684

2. 发明公开

EP0540444A1 CVD diamond or diamond-like carbon for chemical-mechanical polish etch stop 失效
标题翻译： Diamant-oderdiamantähnlicheÄtzstopschichtfürchemisch-mechanisches Polieren。
公开(公告)号：EP0540444A1
公开(公告)日：1993-05-05
申请号：EP92480143.4
申请日：1992-10-09
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Jaso, Mark Anthony , Jones, Paul Bradley , Meyerson, Bernard Steele , Patel, Vishnubhai Vitthalbhai
IPC分类号： H01L21/768 , H01L21/311
CPC分类号： H01L21/31053 , H01L21/76819
摘要： Metallized semiconductor chips, such as are intended for VLSI, are coated with a first layer of SiO2 followed by a second layer of CVD diamond or DLC as an etch stop. The resulting structure is reproducibly and controllably planarized using a chem-mech slurry and an appropriate polishing pad, enabling subsequent layers to be built up similarly.
摘要翻译：诸如用于VLSI的金属化半导体芯片涂覆有第一层SiO 2，随后是第二层CVD金刚石或DLC作为蚀刻停止层。所得到的结构可以使用化学浆料和适当的抛光垫重复地且可控制地平坦化，使得可以类似地构建后续层。

3. 发明授权

EP0540444B1 CVD diamond or diamond-like carbon for chemical-mechanical polish etch stop 失效
标题翻译：钻石或钻石般的蚀刻阻挡层的化学机械抛光
公开(公告)号：EP0540444B1
公开(公告)日：1996-09-25
申请号：EP92480143.4
申请日：1992-10-09
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Jaso, Mark Anthony , Jones, Paul Bradley , Meyerson, Bernard Steele , Patel, Vishnubhai Vitthalbhai
IPC分类号： H01L21/768 , H01L21/311
CPC分类号： H01L21/31053 , H01L21/76819

4. 发明公开

EP0599761A1 A method of forming uniformly thin, isolated silicon mesas on an insulating substrate 失效
标题翻译：一种用于制备绝缘基板上均匀的薄硅台面结构的过程。
公开(公告)号：EP0599761A1
公开(公告)日：1994-06-01
申请号：EP93480116.8
申请日：1993-08-24
申请人： International Business Machines Corporation
发明人： Beyer, Klaus Dietrich , Iyer, Subramanian Srikanteswara , Warnock, James Douglas , Jaso, Mark Anthony , Stiffler, Scott Richard
IPC分类号： H01L21/76 , H01L21/306
CPC分类号： H01L21/3212 , H01L21/76264 , H01L21/76283 , Y10S438/977
摘要： The method of the subject invention comprises the steps of: providing a substrate including an insulator material having a generally planar surface; forming a plurality of mesas of a semiconductor material on the substrate surface, the plurality of mesas spaced by channels extending to the substrate surface, the plurality of mesas including device mesas and dummy mesas; forming a polish-stop structure of at least one selected material over the substrate surface in the channels; polishing the plurality of mesas and stopping on the polish-stop structure whereby the plurality of mesas have the same thickness as the polish-stop structure; and replacing the dummy mesas with an insulator material whereby to electrically isolate the device mesas.
摘要翻译：本主题发明的方法包括以下步骤：提供一基材，包括绝缘体上的材料具有一个基因的反弹平坦表面; 形成在基板表面上的半导体材料的台面的复数，台面的所述多个通道延伸至所述基板的表面，台面的包括设备台面和台面虚设的多个间隔; 上方形成在通道基板表面的至少一个中选择的材料的抛光停止结构; 抛光台面的多元性和停止在抛光停止结构，由此台面的多元性具有相同的厚度作为抛光停止结构; 并与绝缘体材料取代虚设台面从而以电隔离装置台面。

5. 发明授权

EP0774777B1 A method of chemically mechanically polishing an electronic component 失效
标题翻译：一种用于电子部件的化学机械抛光方法
公开(公告)号：EP0774777B1
公开(公告)日：2002-01-16
申请号：EP96307693.0
申请日：1996-10-24
申请人： International Business Machines Corporation
发明人： Armacost, Michael David , Dobuzinsky, David Mark , Gambino, Jeffery Peter , Jaso, Mark Anthony
IPC分类号： H01L21/3105 , H01L21/768
CPC分类号： H01L21/3212

6. 发明公开

EP0794567A2 Process for forming a deep trench-type storage node for a DRAM 失效
标题翻译： Verfahren zur Herstellung eines Speicherknotens mit TiefgrabenstrukturfürDRAM
公开(公告)号：EP0794567A2
公开(公告)日：1997-09-10
申请号：EP97102901.2
申请日：1997-02-21
申请人： SIEMENS AKTIENGESELLSCHAFT , INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Ho, Herbert L. , Srinivasan, Radhika , Halle, Scott D. , Hammerl, Erwin , Dobuzinsky, David M. , Mandelman, Jack A. , Jaso, Mark Anthony
IPC分类号： H01L21/70 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/10861 , H01L21/76232 , H01L27/10832 , H01L28/82 , Y10S438/973
摘要： A simplified method of fabricating a storage node for a deep trench-based DRAM on a semiconductor substrate. The method involves the etching a trench in a surface of the substrate and then forming a layer of dielectric material on a sidewall of the trench the top portion of which is subsequently removed from the sidewall. Next, a layer of oxide is grown on the exposed portion of the sidewall. A portion of this layer of oxide is then removed from the sidewall in order to orient the layer of oxide a predetermined distance from the surface of the substrate. Finally, the trench is filled with a semiconductive material.
摘要翻译：在半导体衬底上制造用于深沟槽型DRAM的存储节点包括蚀刻衬底中的沟槽，在侧壁上形成电介质层，并部分地去除其以暴露侧壁的上部的下部区域，在其上具有层的氧化物生长。然后去除部分氧化物以使该层从基板表面定向给定距离，然后用半导体填充沟槽。还要求保护的是另一种方法，其中节点电介质（20）沉积在侧壁上，生长氧化物环（24），填充有抗蚀剂的沟槽被蚀刻以去除上述的氧化物环的一部分，并且沟槽充满多晶硅（30）。

7. 发明公开

EP0774781A3 Method of forming studs within an insulating layer on a semiconductor wafer 失效
标题翻译：在绝缘层中载体的制造方法，在半导体晶片上
公开(公告)号：EP0774781A3
公开(公告)日：1998-04-08
申请号：EP96308103.9
申请日：1996-11-08
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Gambino, Jeffrey Peter , Jaso, Mark Anthony , Nesbit, Larry Alan
IPC分类号： H01L21/768
CPC分类号： H01L21/3212 , H01L21/76819 , H01L21/7684
摘要： A semiconductor wafer is processed to form interlevel studs of at least two different materials in an insulating layer 150 on the semiconductor wafer. After forming an insulating layer of BPSG on a Front End of the Line (FEOL) structure, the BPSG layer is chem-mech polished. Vias 154 are formed through the BPSG layer in array areas. A thin doped poly layer 156 is deposited on the surface of the BPSG layer. The structure is annealed and vias 160, 162 are formed in support areas. Dopants are implanted into support areas through the vias. After annealing to diffuse implanted dopant, a metal layer 164 is formed on the poly layer. Then, the structure is chem-mech polished back to the poly layer. A final chem-mech polish step removes the poly layer, leaving metal studs in the support areas and poly-lined metal cored studs in the array areas.

8. 发明公开

EP0774781A2 Method of forming studs within an insulating layer on a semiconductor wafer 失效
标题翻译：在绝缘层中载体的制造方法，在半导体晶片上
公开(公告)号：EP0774781A2
公开(公告)日：1997-05-21
申请号：EP96308103.9
申请日：1996-11-08
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Gambino, Jeffrey Peter , Jaso, Mark Anthony , Nesbit, Larry Alan
IPC分类号： H01L21/768
CPC分类号： H01L21/3212 , H01L21/76819 , H01L21/7684
摘要： A semiconductor wafer is processed to form interlevel studs of at least two different materials in an insulating layer 150 on the semiconductor wafer. After forming an insulating layer of BPSG on a Front End of the Line (FEOL) structure, the BPSG layer is chem-mech polished. Vias 154 are formed through the BPSG layer in array areas. A thin doped poly layer 156 is deposited on the surface of the BPSG layer. The structure is annealed and vias 160, 162 are formed in support areas. Dopants are implanted into support areas through the vias. After annealing to diffuse implanted dopant, a metal layer 164 is formed on the poly layer. Then, the structure is chem-mech polished back to the poly layer. A final chem-mech polish step removes the poly layer, leaving metal studs in the support areas and poly-lined metal cored studs in the array areas.
摘要翻译：在半导体晶片上的绝缘层上形成至少两种不同的材料的层间柱，在包括：（a）形成在半导体晶片上的绝缘材料层; （B）平面化的绝缘层; （C）形成穿过绝缘层的通孔的第一组; （D）形成在绝缘层上的第一导电材料层; （E）通过所述第一导电材料层形成通孔的第二组和绝缘层; （F）形成第二导电材料填充的通孔的所述第一和第二组的一个层; （G）去除所述第二导电层，以暴露所述第一导电材料层，检查没有所述第二导电材料仅保留在所述第一和第二通孔群; 及（h）去除所述暴露的第一导电材料层。这样一种被所述方法如上述其中步骤（b）中，（h）和（i）的由化学 - 机械抛光，（c）和（e）中取得被蚀刻和掺杂剂通过第二组注入到晶片通孔和所述晶片（E）之后进行退火。

9. 发明公开

EP0477495A1 Josephson integrated circuit 失效
标题翻译： Integrierter Josephson-Schaltkreis。
公开(公告)号：EP0477495A1
公开(公告)日：1992-04-01
申请号：EP91112385.9
申请日：1991-07-24
申请人： International Business Machines Corporation
发明人： Gallagher, William Joseph , Hu, Chao-Kun , Jaso, Mark Anthony , Ketchen, Mark Benjamin , Kleinsasser, Alan Willis , Pearson, Dale Jonathan
IPC分类号： H01L39/24
CPC分类号： H01L39/2493 , H01L27/18 , Y10S505/728 , Y10S505/82
摘要： A method for fabricating Josephson integrated circuits and the circuit is described incorporating the steps of depositing layers of different materials to form a trilayer Josephson junction, etching to define a plurality of trilayer areas (22, 23, 24), depositing dielectric material thereover, and chemical-mechanical polishing to planarize the dielectric material down to provide a coplanar surface (55) with the tops (56, 57, 58) of the trilayer areas for subsequent interconnection. The invention overcomes the problem of poor quality Josephson junctions, low Vm's, and crevices or gaps in the upper coplanar surface between the trilayer area and the surrounding dielectric material.
摘要翻译：描述了一种用于制造约瑟夫逊集成电路的方法和电路，其结合了沉积不同材料的层以形成三层约瑟夫逊结的步骤，蚀刻以限定多个三面体区域（22,23,24），在其上沉积介电材料，以及化学机械抛光以将介电材料平坦化，以提供与三层区域的顶部（56,57,58）的共面表面（55），用于随后的互连。本发明克服了质量差的约瑟夫逊结，低Vm以及三层区域和周围电介质材料之间的上共面的缝隙或间隙的问题。

10. 发明授权

EP0773580B1 A method of chemically mechanically polishing an electronic component 失效
标题翻译：一种用于电子部件的化学机械抛光方法
公开(公告)号：EP0773580B1
公开(公告)日：2002-01-16
申请号：EP96307618.7
申请日：1996-10-21
申请人： International Business Machines Corporation
发明人： Jaso, Mark Anthony
IPC分类号： H01L21/3105 , H01L21/768
CPC分类号： H01L21/31053

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