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1. 发明公开

EP3392778A1 COMMUNICATION DEVICE, COMMUNICATION METHOD, PROGRAM, AND COMMUNICATION SYSTEM 审中-公开
公开(公告)号：EP3392778A1
公开(公告)日：2018-10-24
申请号：EP16875423.2
申请日：2016-12-02
申请人： Sony Corporation
发明人： LEE Sonfun , TAKAHASHI Hiroo , KOSHISAKA Naohiro
IPC分类号： G06F13/38 , H04L29/06
CPC分类号： G06F13/423 , G06F11/076 , G06F11/1004 , G06F13/4291 , H04L29/06
摘要： The present disclosure relates to a communication apparatus, a communication method, a program, and a communication system that are configured to provide more correct communication.
A master has a sending block for sending data to a slave on a word basis in which data of two bytes are included per one word and a confirmation block for confirming the data to be sent to the slave so as to include the notification information necessary for recognizing presence or absence of a word having invalid data into a signal to be sent to the slave. The slave has a receiving block for receiving the data sent from the master on a word basis and a recognition block for, if the received word is recognized to have invalid data according to the notification information included in the signal transferred from the master, avoiding the execution of the processing based on that invalid data. For example, on the basis of a result of the confirmation of the notification information, the invalid data included in the word recognized to have invalid data is masked. The present technology is applicable to a bus IF through which communication is executed in compliance with the I3C standard, for example.

2. 发明公开

EP3161650A1 METHOD AND APPARATUS OF USB 3.1 RETIMER PRESENCE DETECT AND INDEX 审中-公开
标题翻译： USB 3.1最终存在检测和索引的方法和设备
公开(公告)号：EP3161650A1
公开(公告)日：2017-05-03
申请号：EP15811333.2
申请日：2015-05-27
申请人： Intel Corporation
发明人： CHEN, Huimin , HECK, Howard L.
IPC分类号： G06F13/40 , G06F13/42
CPC分类号： G06F13/423 , G05B2219/25181 , G06F13/4045 , G06F13/4256 , G06F2213/0052 , H04B3/58 , H04B10/29 , H04B2203/5479 , Y02B70/123 , Y02B70/126 , Y02D10/14 , Y02D10/151
摘要： An apparatus for retimer presence detection is described herein. The apparatus includes at least one retimer, wherein an algorithm is to enable the at least one retimer to announce its presence by asserting a bit of a presence message during link initialization. The at least one retimer can declare an index and is accessible via the index.
摘要翻译：这里描述了用于重定时器存在检测的设备。该装置包括至少一个重定时器，其中算法是通过在链路初始化期间断言存在消息的位来使至少一个重定时器能够通告其存在。至少一个重定时器可以声明一个索引并且可以通过该索引访问。

3. 发明公开

EP2865163A4 PROVIDING A SERIAL PROTOCOL FOR A BIDIRECTIONAL SERIAL INTERCONNECT 审中-公开
标题翻译：提供串行协议进行双向串行链路
公开(公告)号：EP2865163A4
公开(公告)日：2016-01-20
申请号：EP13809192
申请日：2013-06-19
申请人： INTEL CORP
发明人： HARRIMAN DAVID J , MORRISS JEFF C
IPC分类号： H04L29/06 , G06F1/12 , G06F11/08 , G06F13/18 , G06F13/42 , H04L1/00
CPC分类号： G06F13/423 , G06F1/12 , G06F11/08 , G06F13/4291 , G08C25/00 , H04L1/0061 , Y02B60/1228 , Y02B60/1235 , Y02D10/14 , Y02D10/151
摘要： In one embodiment, the present invention includes a host controller with transmit logic to prepare data into a data packet for communication along an interconnect and to transmit the data packet. This data packet may include a preamble portion having a first predetermined value, a content portion including the data and having a plurality of symbols each including a start bit separate from the data, an error detection portion including an inverted version of the content portion, and a postamble portion having a second predetermined value. Other embodiments are described and claimed.

4. 发明公开

EP2843486A3 Verfahren und Vorrichtung zum Synchronisieren einer Steuereinheit und mindestens einer zugeordneten Peripherieeinheit 有权
标题翻译：用于同步控制单元和至少一个的方法和装置相关联的外围单元
公开(公告)号：EP2843486A3
公开(公告)日：2015-04-01
申请号：EP14169606.2
申请日：2014-05-23
申请人： Dr. JOHANNES HEIDENHAIN GmbH
发明人： Wastlhuber, Robert
IPC分类号： G05B19/042
CPC分类号： G06F13/423 , G05B19/0426
摘要： Die Erfindung betrifft ein Verfahren zum Synchronisieren einer Steuereinheit und mindestens einer Aktoren und/oder Sensoren aufweisenden Peripherieeinheit, die über eine serielle Schnittstelle (3) Daten miteinander austauschen, wobei die Steuereinheit (1) Daten an die mindestens eine Peripherieeinheit (2) sendet, die in der Peripherieeinheit (2) zum Betreiben der Aktoren (22) und/oder Sensoren (23) bearbeitet werden, und wobei zur Synchronisation mindestens ein Synchronisationszeichen (105) von der Steuereinheit (1) zu der Peripherieeinheit (2) übertragen wird. Dabei wird das Synchronisationszeichen (105) aufseiten der Steuereinheit an eine erste Datenfolge (101) eines von der Steuereinheit (1) an die Peripherieeinheit (2) zu sendenden Datenstroms angehängt und aufseiten der Steuereinheit (1) das Senden einer nach der ersten Datenfolge (101) zu übertragenden zweiten Datenfolge (102) zeitlich verzögert, so dass die zweite Datenfolge (102) auf das Synchronisationszeichen (105) folgend von der Steuereinheit (1) an die Peripherieeinheit (2) gesandt wird.
摘要翻译：在用于同步控制单元和通过一个串行接口具有致动器和/或传感器，控制单元和所述外围单元交换数据海誓山盟至少一个外围单元的方法。所述控制单元将数据发送到至少一个外围单元所有这一切都在周边单元处理用于致动器和/或传感器的外科手术，和至少一个同步字符是从控制单元的反式mitted到用于同步的外围单元。在这种情况下，同步字符由控制单元追加到数据流中的第一数据序列是从控制单元的反式mitted到外围单元，和第二数据序列的传输是第一数据序列之后的反式mitted 被延迟在时间上的控制单元的一部分，所以没有第二数据序列被反式由控制单元mitted到外围单元继同步字符。

5. 发明公开

EP2800005A1 Method and apparatus for synchronising the local time of a plurality of instruments 审中-公开
标题翻译： Verfahren und Vorrichtung zur Synchronisierung der lokalen Zeit mehrerer Instrumente
公开(公告)号：EP2800005A1
公开(公告)日：2014-11-05
申请号：EP14170487.4
申请日：2010-05-20
申请人： Chronologic Pty Limited
发明人： Foster, Peter Graham
IPC分类号： G06F13/40 , G06F13/42 , G06F1/12 , H04L7/04
CPC分类号： G06F13/423 , G06F1/08 , G06F1/12 , G06F11/3027 , G06F13/10 , G06F13/4022 , G06F13/4027 , G06F13/405 , G06F13/4282 , G06F2213/0042 , H04L7/04 , H04L7/08
摘要： A method of determining the downstream propagation time of signals from a selected point in a USB network across one or more USB cables and one or more USB Hubs to a first SuperSpeed USB device of a plurality of SuperSpeed USB devices, the method comprising: ensuring that said first SuperSpeed USB device is in link state U0; ensuring that said SuperSpeed USB devices other than said first SuperSpeed USB device are not in link state U0; ensuring that no request is made to change the link state of any links in a USB network branch spanned by said selected point and said first SuperSpeed USB Device; performing a plurality of round trip propagation time measurements for said first SuperSpeed USB device.
摘要翻译：一种确定来自USB网络中的选定点的信号的一个或多个USB电缆和一个或多个USB集线器的信号的下行传播时间到多个超高速USB设备的第一超速USB设备的方法，所述方法包括：确保说第一个SuperSpeed USB设备处于链路状态U0; 确保除了所述第一SuperSpeed USB设备之外的所述SuperSpeed USB设备不处于链路状态U0; 确保不要求改变由所述选定点和所述第一超速USB设备跨越的USB网络分支中的任何链路的链路状态; 对所述第一SuperSpeed USB设备执行多个往返传播时间测量。

6. 发明公开

EP2800004A1 Synchronous network of superspeed and non-superspeed USB devices 审中-公开
标题翻译：同步Netzwerk von Superspeed- und Nicht-Superspeed-USB-Vorrichtungen
公开(公告)号：EP2800004A1
公开(公告)日：2014-11-05
申请号：EP14165614.0
申请日：2010-05-20
申请人： Chronologic Pty Limited
发明人： Foster, Peter Graham
IPC分类号： G06F13/40 , G06F13/42 , G06F1/12 , H04L7/04
CPC分类号： G06F13/423 , G06F1/08 , G06F1/12 , G06F11/3027 , G06F13/10 , G06F13/4022 , G06F13/4027 , G06F13/405 , G06F13/4282 , G06F2213/0042 , H04L7/04 , H04L7/08
摘要： A method of synchronising the operation of a plurality of SuperSpeed USB devices and a plurality of non-SuperSpeed USB devices, the method comprising: establishing a SuperSpeed synchronisation channel for each of the plurality of SuperSpeed USB devices; establishing a non-SuperSpeed synchronisation channel for each of the plurality of non-SuperSpeed USB devices; synchronising a respective local clock of each of the plurality of SuperSpeed USB devices; synchronising a respective local clock of each of the plurality of non-SuperSpeed USB devices; and synchronising the SuperSpeed and non-SuperSpeed synchronisation channels so that the SuperSpeed and non-SuperSpeed devices can operate in synchrony.
摘要翻译：一种使多个SuperSpeed USB设备和多个非SuperSpeed USB设备的操作同步的方法，所述方法包括：为所述多个SuperSpeed USB设备中的每一个建立超速同步信道; 为所述多个非SuperSpeed USB设备中的每一个建立非超速同步信道; 使多个SuperSpeed USB设备中的每一个的相应本地时钟同步; 使所述多个非SuperSpeed USB设备中的每一个的相应本地时钟同步; 并同步SuperSpeed和非SuperSpeed同步通道，使SuperSpeed和非SuperSpeed设备可以同步运行。

7. 发明公开

EP2750046A3 Media peripheral interface, electronic device with media peripheral interface, and communication method between processor and peripheral device 有权
标题翻译：外围媒体接口，与所述处理器和外围设备之间的圆周媒体接口和通信方法的电子设备
公开(公告)号：EP2750046A3
公开(公告)日：2014-10-15
申请号：EP13199116.8
申请日：2013-12-20
申请人： MediaTek, Inc
发明人： Chen, Tsung-Huang , Tu, Li-Chun , Chao, Wen-Chi
IPC分类号： G06F13/42
CPC分类号： G06F1/08 , G06F13/423
摘要： A media peripheral interface for communication between a processor and a peripheral device includes a clock port, a plurality of data I/Os, and a data strobe port. The clock port is operative to transfer a clock signal to the peripheral device. The data I/Os are provided for command transfer to the peripheral device and for data transfer to and from the peripheral device. The data strobe port is operative to transfer a data strobe signal to or from the peripheral device according to an instruction that the processor issues to the peripheral device. According to the clock signal, command information transferred via the data I/Os is captured. According to rising edges and falling edges of the data strobe signal, data transferred via the data I/Os are captured.

8. 发明授权

EP2433194B1 COMPOUND UNIVERSAL SERIAL BUS ARCHITECTURE PROVIDING PRECISION SYNCHRONISATION TO AN EXTERNAL TIMEBASE 有权
标题翻译：接口通用SERIENBUSARCHITEKTUR FOR提供高精度的同步AN外部时基
公开(公告)号：EP2433194B1
公开(公告)日：2014-08-13
申请号：EP10777227.9
申请日：2010-05-20
申请人： Chronologic Pty Ltd
发明人： FOSTER, Peter Graham
IPC分类号： G06F1/12 , G06F13/42 , H04L7/00
CPC分类号： G06F13/423 , G06F1/08 , G06F1/12 , G06F11/3027 , G06F13/10 , G06F13/4022 , G06F13/4027 , G06F13/405 , G06F13/4282 , G06F2213/0042 , H04L7/04 , H04L7/08

9. 发明公开

EP2750046A2 Media peripheral interface, electronic device with media peripheral interface, and communication method between processor and peripheral device 有权
标题翻译：外围媒体接口，与所述处理器和外围设备之间的圆周媒体接口和通信方法的电子设备
公开(公告)号：EP2750046A2
公开(公告)日：2014-07-02
申请号：EP13199116.8
申请日：2013-12-20
申请人： MediaTek, Inc
发明人： Chen, Tsung-Huang , Tu, Li-Chun , Chao, Wen-Chi
IPC分类号： G06F13/42
CPC分类号： G06F1/08 , G06F13/423
摘要： A media peripheral interface for communication between a processor and a peripheral device includes a clock port, a plurality of data I/Os, and a data strobe port. The clock port is operative to transfer a clock signal to the peripheral device. The data I/Os are provided for command transfer to the peripheral device and for data transfer to and from the peripheral device. The data strobe port is operative to transfer a data strobe signal to or from the peripheral device according to an instruction that the processor issues to the peripheral device. According to the clock signal, command information transferred via the data I/Os is captured. According to rising edges and falling edges of the data strobe signal, data transferred via the data I/Os are captured.
摘要翻译：用于在处理器和外围设备之间的通信的媒体外围接口包括时钟端口，数据I / O的多个，并且一个数据选通端口，时钟端口可操作以一个时钟信号传送到所述外围设备。数据I / O被设置用于命令传输到所述外围设备和用于数据传输到和从外围设备。数据选通信端口可操作，用于将数据选通信号传输到或从外围设备做了处理器问题到所述外围设备，以gemäß指令。。根据该时钟信号，命令经由数据I传送的信息/ O的被捕获。。根据上升沿和数据选通信号的下降沿，经由数据I传送的数据/ O被捕获。

10. 发明授权

EP2433195B1 JITTER REDUCTION METHOD AND APPARATUS FOR DISTRIBUTED SYNCHRONISED CLOCK ARCHITECTURE 有权
标题翻译：用于分布式同步时钟架构SURGE还原的方法和装置
公开(公告)号：EP2433195B1
公开(公告)日：2014-01-22
申请号：EP10777232.9
申请日：2010-05-20
申请人： Chronologic Pty Ltd
发明人： FOSTER, Peter Graham , KOUZNETSOV, Alex
IPC分类号： G06F1/12 , G06F13/14 , G06F1/10 , H04L7/08
CPC分类号： G06F13/423 , G06F1/08 , G06F1/12 , G06F11/3027 , G06F13/10 , G06F13/4022 , G06F13/4027 , G06F13/405 , G06F13/4282 , G06F2213/0042 , H04L7/04 , H04L7/08

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