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1. 发明授权

EP0399191B1 Fabrication process for a self-aligned, lightly-doped drain-source trench transistor 失效
标题翻译：一种用于生产具有在沟槽轻掺杂漏极和源极晶体管sichselbstjustierenden方法。
公开(公告)号：EP0399191B1
公开(公告)日：1994-08-24
申请号：EP90106685.2
申请日：1990-04-06
申请人： International Business Machines Corporation
发明人： Dhong, Sang H. , Hwang, Wei , Lu, Nicky C. C.
IPC分类号： H01L29/784 , H01L27/108 , H01L21/82
CPC分类号： H01L27/10844 , H01L21/2236 , H01L27/10838 , H01L27/112 , H01L29/7827 , H01L29/7834

2. 发明公开

EP0522361A2 Power saving sensing circuits for dynamic random access memory 失效
标题翻译： EnergiesparschaltungfürAbfühlschaltungenfürDRAM。
公开(公告)号：EP0522361A2
公开(公告)日：1993-01-13
申请号：EP92110725.6
申请日：1992-06-25
申请人： International Business Machines Corporation
发明人： Dhong, Sang H. , Terman, Lewis M.
IPC分类号： G11C11/409
CPC分类号： G11C11/4091
摘要： A sensing circuit for a dynamic random access memory structure is disclosed having first and second bit lines (22A, 22B), one of the bit lines being a reference bit line which is held at a precharge voltage when a sense amplifier (40) in the sensing circuit is latched. The sense amplifier (40) includes first and second nodes (44, 42) and first, second, third and fourth transistor devices, the first and second transistor devices form an N-device cross-coupled pair (43) and the third and fourth transistor devices form a P-device cross-coupled pair (41). The first node (44) is connected to the first bit line (22A) and to the second and fourth transistor devices, and the second node (42) is connected to the first and third transistor devices. A first isolation transistor device (10) is connected to the first bit line (22A) and a second isolation transistor device (12) is connected to the second bit line (22B). A first clock signal line (32) is connected to the first isolation transistor device (10) and a second lock signal line (34) is connected to the second isolation transistor device (12). A first equalization transistor device (20) is connected to the first bit line (22A) and a second equalization transistor device (18) is connected to the second bit line (22B), a voltage signal line having a voltage value V EQ thereon is connected to the first and second equalization transistor devices (20, 18), and a third clock signal line (24) is connected to the first equalization device (20). A fourth clock signal line (26) is connected to the second equalization transistor device (18). A fifth clock signal line (30) is connected to the first and second N-devices, a sixth clock signal line (28) is connected to the third and fourth P-devices. The first, second, third, fourth and fifth and sixth clock signal lines have clock signals thereon which occur during a time sequence for pre-charging the first and second nodes to a precharge voltage value V EQ .
摘要翻译：公开了一种用于动态随机存取存储器结构的感测电路，其具有第一和第二位线（22A，22B），其中一个位线是当在位置线中的读出放大器（40）处于预充电电压时保持在预充电电压的参考位线感测电路被锁存。读出放大器（40）包括第一和第二节点（44,42）以及第一，第二，第三和第四晶体管器件，第一和第二晶体管器件形成N器件交叉耦合对（43），第三和第四晶体管器件晶体管器件形成P器件交叉耦合对（41）。第一节点（44）连接到第一位线（22A）和第二和第四晶体管器件，第二节点（42）连接到第一和第三晶体管器件。第一隔离晶体管器件（10）连接到第一位线（22A），第二隔离晶体管器件（12）连接到第二位线（22B）。第一时钟信号线（32）连接到第一隔离晶体管器件（10），第二锁定信号线（34）连接到第二隔离晶体管器件（12）。第一均衡晶体管器件（20）连接到第一位线（22A），第二均衡晶体管器件（18）连接到第二位线（22B），其上具有电压值VEQ的电压信号线被连接到第一和第二均衡晶体管器件（20,18），并且第三时钟信号线（24）连接到第一均衡器件（20）。第四时钟信号线（26）连接到第二均衡晶体管器件（18）。第五时钟信号线（30）连接到第一和第二N器件，第六时钟信号线（28）连接到第三和第四P器件。第一，第二，第三，第四和第五和第六时钟信号线在其上具有时钟信号，其在用于将第一和第二节点预充电到预充电电压值VEQ的时间序列期间发生。

3. 发明公开

EP0354348A3 CMOS-transistor and one-capacitor dram cell and fabrication process therefor 失效
标题翻译： CMOS晶体管和单电容器DRAM单元及其制造工艺
公开(公告)号：EP0354348A3
公开(公告)日：1991-06-05
申请号：EP89112325.9
申请日：1989-07-06
申请人： International Business Machines Corporation
发明人： Dhong, Sang H. , Henkels, Walter H. , Lu, Nicky C.
IPC分类号： G11C11/404 , G11C11/24
CPC分类号： G11C11/404 , H01L27/0688 , H01L27/108
摘要： A complementary MOS one-capacitor dynamic RAM cell (e.g. 38) operates with a non-boosted wordline without a threshold loss problem. It includes one storage capacitor (30) and n- and p-type transfer devices (10, 12) connected to the storage capacitor which function as two complementary transistor devices having gates controlled by complementary signals on the RAM wordlines (26, 28).

4. 发明公开

EP0366882A2 An ultra dense DRAM cell array and its method of fabrication 失效
标题翻译： Ultradichte DRAM-Zelle-Matrix和ihr Herstellungsverfahren。
公开(公告)号：EP0366882A2
公开(公告)日：1990-05-09
申请号：EP89114239.0
申请日：1989-08-02
申请人： International Business Machines Corporation
发明人： Chin, Daeje , Dhong, Sang H.
IPC分类号： H01L21/82 , H01L21/76 , H01L27/108
CPC分类号： H01L27/10864 , H01L21/3065 , H01L27/10841
摘要： This invention relates generally to ultra dense dynamic random access semiconductor memory arrays. It also relates to a method of fabricating such arrays using a plurality of etch and refill steps which includes a differential etching step which is a key step in forming insulating conduits which themselves are adapted to hold a pair of field effect transistor gates (6) of the adjacent transfer devices of the one device memory cells. The differential etch step provides spaced apart device regions and an insulation region of reduced height between the trenches which space apart the memory cells. The resulting structure includes a plurality of rows of vertically arranged field effect transistors wherein the substrate (8, 11, 12) effectively acts as a counterelectrode surrounding the insulated drain regions (5) of each of the one device memory cells. A pair of gates (6) are disposed in insulating conduits (15) which run perpendicular to the rows of memory cells. Each gate (6) in a conduit is disposed in insulated spaced relationship with a memory cell channel region (4) which, in response to signals on the gate turns on a column of channel regions (4) so as to permit the entry of charge into a selected storage region when a bitline (16) associated with a particular cell (2) is energized. The resulting array shows rows of pairs of memory cells (2) wherein each cell of a pair is spaced from the other by a portion (12) of the substrate acting as a counterelectrode and each of the pairs of memory cells is similarly separated from an adjacent pair by regions (11) of conductive material acting as a counterelectrode.
摘要翻译：本发明一般涉及超密度动态随机存取半导体存储器阵列。它还涉及使用多个蚀刻和再填充步骤制造这种阵列的方法，其包括差分蚀刻步骤，其是形成绝缘导管的关键步骤，它们本身适于保持一对场效应晶体管栅极（6）一个设备存储单元的相邻传输设备。差分蚀刻步骤提供间隔开的器件区域和间隔开存储器单元的沟槽之间的高度减小的绝缘区域。所得到的结构包括多行垂直布置的场效应晶体管，其中衬底（8,11,12）有效地用作围绕每个器件存储单元的绝缘漏区（5）的反电极。一对门（6）设置在垂直于存储单元行行进的绝缘导管（15）中。管道中的每个门（6）与存储器单元通道区域（4）以绝对间隔的关系设置，所述存储器单元通道区域（4）响应于栅极上的信号转动在通道区域（4）的列上，以允许进入电荷当与特定单元（2）相关联的位线（16）被通电时，进入选定的存储区域。所得到的阵列示出了一对存储单元（2），其中一对的每个单元通过作为反电极的衬底的一部分（12）彼此间隔开，并且每对存储单元类似地与相邻的一对作为反电极的导电材料的区域（11）。

5. 发明授权

EP0535325B1 Voltage generator for a memory array 失效
标题翻译：用于存储器阵列电压发生器
公开(公告)号：EP0535325B1
公开(公告)日：1998-10-28
申请号：EP92113155.3
申请日：1992-08-01
申请人： International Business Machines Corporation
发明人： Dhong, Sang H. , Shin, Hyun J. , Hwang, Wei
IPC分类号： G11C5/14
CPC分类号： G11C8/08 , G11C5/147

6. 发明公开

EP0535325A3 Voltage generator for a memory array 失效
标题翻译：用于存储阵列的电压发生器
公开(公告)号：EP0535325A3
公开(公告)日：1995-01-18
申请号：EP92113155.3
申请日：1992-08-01
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Dhong, Sang H. , Shin, Hyun J. , Hwang, Wei
IPC分类号： G11C5/14
CPC分类号： G11C8/08 , G11C5/147
摘要： A voltage generator comprising a regulator for controlling said on-chip generator which produces a boost voltage V BST supplied to one of two inputs to each of a plurality of word line drivers in a memory array, the other input to each of said word line drivers receiving a power supply voltage V DD . Said voltage regulator comprising:
means for generating a reference voltage V REF ;
first differential means (33) for producing a transition voltage V X from said reference voltage V REF and said power supply voltage VDD, said transition voltage being representative of a fluctuation in said power supply voltage;
first transistor means (QP3) for comparing said power supply voltage V DD with said boost voltage V BST ;
second transistor (QP5) means for comparing said transition voltage V X with said reference voltage V REF ; and
a latching comparator (44) coupled to receive the signal outputs from said first transistor (QP3) and said second transistor (QP5), said latching comparator outputting a boost voltage control signal for said on-chip voltage generator, said control signal operating to define the following boost voltage: V BST = - V REF + V DD - V X .

7. 发明公开

EP0522361A3 Power saving sensing circuits for dynamic random access memory 失效
标题翻译：用于动态随机存取存储器的节能感测电路
公开(公告)号：EP0522361A3
公开(公告)日：1994-02-16
申请号：EP92110725.6
申请日：1992-06-25
申请人： International Business Machines Corporation
发明人： Dhong, Sang H. , Terman, Lewis M.
IPC分类号： G11C11/409
CPC分类号： G11C11/4091
摘要： A sensing circuit for a dynamic random access memory structure is disclosed having first and second bit lines (22A, 22B), one of the bit lines being a reference bit line which is held at a precharge voltage when a sense amplifier (40) in the sensing circuit is latched. The sense amplifier (40) includes first and second nodes (44, 42) and first, second, third and fourth transistor devices, the first and second transistor devices form an N-device cross-coupled pair (43) and the third and fourth transistor devices form a P-device cross-coupled pair (41). The first node (44) is connected to the first bit line (22A) and to the second and fourth transistor devices, and the second node (42) is connected to the first and third transistor devices. A first isolation transistor device (10) is connected to the first bit line (22A) and a second isolation transistor device (12) is connected to the second bit line (22B). A first clock signal line (32) is connected to the first isolation transistor device (10) and a second lock signal line (34) is connected to the second isolation transistor device (12). A first equalization transistor device (20) is connected to the first bit line (22A) and a second equalization transistor device (18) is connected to the second bit line (22B), a voltage signal line having a voltage value V EQ thereon is connected to the first and second equalization transistor devices (20, 18), and a third clock signal line (24) is connected to the first equalization device (20). A fourth clock signal line (26) is connected to the second equalization transistor device (18). A fifth clock signal line (30) is connected to the first and second N-devices, a sixth clock signal line (28) is connected to the third and fourth P-devices. The first, second, third, fourth and fifth and sixth clock signal lines have clock signals thereon which occur during a time sequence for pre-charging the first and second nodes to a precharge voltage value V EQ .
摘要翻译：公开了一种用于动态随机存取存储器结构的读出电路，其具有第一和第二位线（22A，22B），其中一个位线是基准位线，当读出放大器（40）处于感测电路被锁存。读出放大器（40）包括第一和第二节点（44,42）以及第一，第二，第三和第四晶体管器件，第一和第二晶体管器件形成N器件交叉耦合对（43），第三和第四晶体管器件形成P器件交叉耦合对（41）。第一节点（44）连接到第一位线（22A）并连接到第二和第四晶体管器件，并且第二节点（42）连接到第一和第三晶体管器件。第一隔离晶体管器件（10）连接到第一位线（22A）并且第二隔离晶体管器件（12）连接到第二位线（22B）。第一时钟信号线（32）连接到第一隔离晶体管器件（10），第二锁定信号线（34）连接到第二隔离晶体管器件（12）。第一均衡晶体管器件（20）连接到第一位线（22A），第二均衡晶体管器件（18）连接到第二位线（22B），其上连接有电压值VEQ的电压信号线到第一和第二均衡晶体管器件（20,18），第三时钟信号线（24）连接到第一均衡器件（20）。第四时钟信号线（26）连接到第二均衡晶体管器件（18）。第五时钟信号线（30）连接到第一和第二N器件，第六时钟信号线（28）连接到第三和第四P器件。第一，第二，第三，第四和第五和第六时钟信号线上具有时钟信号，其在用于将第一和第二节点预充电到预充电电压值VEQ的时间序列期间发生。

8. 发明授权

EP0463459B1 Method for fabricating a mesa transistor-trench capacitor memory cell structure 失效
标题翻译：一种制备严重Mesatransistor电容器存储器单元结构的方法。
公开(公告)号：EP0463459B1
公开(公告)日：1993-12-15
申请号：EP91109555.2
申请日：1991-06-11
申请人： International Business Machines Corporation
发明人： Dhong, Sang H. , Hwang, Wei
IPC分类号： H01L21/82
CPC分类号： H01L27/10844

9. 发明公开

EP0498251A3 Word line driver circuit for dynamic random access memories 失效
标题翻译：用于动态随机存取存储器的字线驱动电路
公开(公告)号：EP0498251A3
公开(公告)日：1993-11-24
申请号：EP92101270.4
申请日：1992-01-27
申请人： International Business Machines Corporation
发明人： Bronner, Gary B. , Dhong, Sang H. , Hwang, Wei
IPC分类号： G11C11/408
CPC分类号： G11C11/4085 , G11C11/4087
摘要： A wordline driver circuit for reading the contents of a Dynamic Random Access Memory (DRAM). The circuit is implemented in CMOS and is capable of pulling the word-lines (10) to a negative potential with respect to the substrate, thereby decreasing the access time. An NMOS pull-down transistor channel (24) is implemented as a P-well within an N-well. Applying a negative potential to the source of the pull-down transistor (24) permits the transistor to be switched so that a negative potential is applied to the wordline (10) when the NMOS pull-down transistor is gated into conduction. A PMOS pull-up transistor (23) is serially connected to the NMOS pull-down transistor drain, permitting the wordline (10) to be driven positively.

10. 发明公开

EP0498251A2 Word line driver circuit for dynamic random access memories 失效
标题翻译： Wortleitungstreiberschaltungfürdynamische Direktzugriffspeicher。
公开(公告)号：EP0498251A2
公开(公告)日：1992-08-12
申请号：EP92101270.4
申请日：1992-01-27
申请人： International Business Machines Corporation
发明人： Bronner, Gary B. , Dhong, Sang H. , Hwang, Wei
IPC分类号： G11C11/408
CPC分类号： G11C11/4085 , G11C11/4087
摘要： A wordline driver circuit for reading the contents of a Dynamic Random Access Memory (DRAM). The circuit is implemented in CMOS and is capable of pulling the word-lines (10) to a negative potential with respect to the substrate, thereby decreasing the access time. An NMOS pull-down transistor channel (24) is implemented as a P-well within an N-well. Applying a negative potential to the source of the pull-down transistor (24) permits the transistor to be switched so that a negative potential is applied to the wordline (10) when the NMOS pull-down transistor is gated into conduction. A PMOS pull-up transistor (23) is serially connected to the NMOS pull-down transistor drain, permitting the wordline (10) to be driven positively.
摘要翻译：用于读取动态随机存取存储器（DRAM）的内容的字线驱动器电路。电路采用CMOS实现，能够将字线（10）相对于基板拉到负电位，从而减少访问时间。 NMOS下拉晶体管通道（24）被实现为N阱内的P阱。将负电位施加到下拉晶体管（24）的源极允许切换晶体管，使得当NMOS下拉晶体管选通导通时，负电位施加到字线（10）。 PMOS上拉晶体管（23）串联连接到NMOS下拉晶体管漏极，允许字线（10）被正向驱动。

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