专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明公开

EP4270469A1 POWER SEMICONDUCTOR MODULE 审中-公开
公开(公告)号：EP4270469A1
公开(公告)日：2023-11-01
申请号：EP22170731.8
申请日：2022-04-29
申请人： Infineon Technologies AG
发明人： LUDWIG, Marco , GOLDAMMER, Martin
IPC分类号： H01L23/24 , H01L23/04
摘要： A power semiconductor module arrangement comprises a substrate comprising a dielectric insulation layer and a first metallization layer attached to the dielectric insulation layer, at least one semiconductor body arranged on the first metallization layer, a housing at least partly enclosing the substrate, the housing comprising a plurality of sidewalls and a lid, a casting compound formed of a first material and partly filling the housing, thereby covering the substrate and the at least one semiconductor body arranged thereon, a first element extending from the lid of the housing into the casting compound in a direction towards the substrate, and a detaining element arranged between the first element and at least one of the plurality of sidewalls of the housing, and configured to prevent traces of the first material wetting the lid of the housing from flowing along the lid from the first element to the one or more sidewalls.

2. 发明公开

EP4276888A1 METHOD FOR PRODUCING A POWER SEMICONDUCTOR MODULE 审中-公开
公开(公告)号：EP4276888A1
公开(公告)日：2023-11-15
申请号：EP22172217.6
申请日：2022-05-09
申请人： Infineon Technologies AG
发明人： GOLDAMMER, Martin , EHLERS, Carsten , NOLTEN, Ulrich , STEININGER, Christian
IPC分类号： H01L21/50 , H01L23/04 , H01L23/053 , H01L23/24 , H01L25/07 , H01L21/54 , H01L23/373 , H01L23/057 , H01L23/498
摘要： A method comprises pouring a liquid, semi-liquid or viscous material into a cavity formed by sidewalls of a housing, thereby covering a substrate that is arranged in the cavity formed by the sidewalls, arranging a lid on the sidewalls, thereby covering the cavity formed by the sidewalls, wherein the lid comprises at least one functional element that extends from the lid into the liquid, semi-liquid or viscous material in a direction towards the substrate once the lid is in its final mounting position, and curing the liquid, semi-liquid or viscous material in order to form a casting compound.

3. 发明公开

EP3889321A1 METHOD FOR PRODUCING A SEMICONDUCTOR SUBSTRATE ARRANGEMENT 审中-公开
公开(公告)号：EP3889321A1
公开(公告)日：2021-10-06
申请号：EP21151070.6
申请日：2020-03-24
申请人： Infineon Technologies AG
发明人： GOLDAMMER, Martin , RIMBERT-RIVIERE, Charles , LOTTSPEICH, Lydia , WILKE, Ulrich
IPC分类号： C23C30/00 , C23C14/04 , C23C14/06 , H01L21/02 , H01L23/14 , H01L23/15 , H01L23/373 , H01L23/498 , H01L23/538 , H01L25/00 , H01L27/00
摘要： A method for forming semiconductor substrate arrangement comprises forming a mask on a semiconductor substrate, the semiconductor substrate comprising a dielectric insulation layer, and a first metallization layer arranged on the dielectric insulation layer, and the mask comprising at least one opening, wherein the first metallization layer is arranged between the mask and the dielectric insulation layer. The method further comprises forming a layer of electrically conductive coating on the first metallization layer, wherein the layer of electrically conductive coating is formed in the at least one opening on those regions of the first metallization layer that are not covered by the mask, and, after forming the layer of electrically conductive coating, removing the mask from the semiconductor substrate. Forming the mask comprises either applying an even layer of material on the first metallization layer such that a thickness of the mask in a vertical direction in a region adjacent to the edges of the mask equals a thickness in the vertical direction of regions of the mask further away from the edges, or applying the material of the mask on the first metallization layer such that the thickness of the mask in the region adjacent to the edges of the mask is greater than the thickness of the regions of the mask further away from the edges, wherein the vertical direction is perpendicular to a top surface of the semiconductor substrate.

4. 发明公开

EP3885467A1 SEMICONDUCTOR SUBSTRATE ARRANGEMENT 审中-公开
公开(公告)号：EP3885467A1
公开(公告)日：2021-09-29
申请号：EP20165192.4
申请日：2020-03-24
申请人： Infineon Technologies AG
发明人： GOLDAMMER, Martin , RIMBERT-RIVIERE, Charles , LOTTSPEICH, Lydia , WILKE, Ulrich
IPC分类号： C23C30/00 , C23C14/04 , C23C14/06 , H01L21/02 , H01L23/14 , H01L23/15 , H01L23/373 , H01L23/498 , H01L23/538 , H01L25/00 , H01L27/00
摘要： A semiconductor substrate arrangement comprises a semiconductor substrate (10) comprising a dielectric insulation layer (11) and a first metallization layer (111) attached to the dielectric insulation layer (11), wherein the first metallization layer (111) is arranged on the dielectric insulation layer (11) in a vertical direction (z). The semiconductor substrate arrangement further comprises an electrically conductive coating (20) arranged on the first metallization layer (111) in the vertical direction (z) such that the first metallization layer (111) is arranged between the electrically conductive coating (20) and the dielectric insulation layer (11). In in a horizontal plane (x-y) within a first distance (x1) from the outer perimeter of the electrically conductive coating (20), the first metallization layer (111) does not comprise any cavities or trenches (40), or only cavities or trenches (40) having a maximum width (w40) in a horizontal direction (x, y) that is less than 10µm and a maximum depth (d40) in the vertical direction (z) that is less than 3µm.

5. 发明公开

EP4270454A3 POWER SEMICONDUCTOR MODULE COMPRISING A FIRST AND A SECOND COMPARTMENT AND METHOD FOR FABRICATING THE SAME 审中-公开
公开(公告)号：EP4270454A3
公开(公告)日：2023-11-22
申请号：EP23168313.7
申请日：2023-04-17
申请人： Infineon Technologies AG
发明人： HARTUNG, Hans , GOLDAMMER, Martin , EHLERS, Carsten , ENGELKEMEIER, Katja , BOENIG, Guido
IPC分类号： H01L21/56 , H01L23/24 , H01L23/31 , H01L21/54 , H01L23/16
摘要： A power semiconductor module comprises: a power semiconductor die arranged on a power substrate, a housing enclosing the power semiconductor die and the power substrate, wherein an interior volume formed by the housing is divided by interior walls into at least a first compartment and a second compartment, wherein the power semiconductor die is arranged within the first compartment, a first encapsulation material encapsulating the power semiconductor die and at least partially filling the first compartment, and a second encapsulation material different from the first encapsulation material, the second encapsulation material encapsulating the first encapsulation material and at least partially filling the second compartment, wherein the first encapsulation material is arranged within the first compartment but not within the second compartment.

6. 发明公开

EP4270466A1 POWER SEMICONDUCTOR MODULE ARRANGEMENTS AND METHODS FOR PRODUCING POWER SEMICONDUCTOR MODULE ARRANGEMENTS 审中-公开
公开(公告)号：EP4270466A1
公开(公告)日：2023-11-01
申请号：EP22169656.0
申请日：2022-04-25
申请人： Infineon Technologies AG
发明人： ARENS, Andre , GOLDAMMER, Martin
IPC分类号： H01L23/053 , H01L23/24 , H01L25/07
摘要： A power semiconductor module arrangement comprises, a housing comprising sidewalls, a lid, and one or more protrusions, a substrate arranged inside the housing or forming a bottom of the housing, a plurality of electronic or electrically conducting components arranged on the substrate, and an encapsulant partly filling the interior of the housing, thereby covering the substrate, wherein each of the one or more protrusions extends from the lid of the housing in a vertical direction towards the substrate, wherein the vertical direction is a direction perpendicular to the substrate and the lid, a lower end of each of the one or more protrusions is either arranged directly above a separate one of the plurality of electronic or electrically conducting components, or within a defined radius around a separate one of the plurality of electronic or electrically conducting components, wherein the defined radius is less than 2mm, and wherein the lower end of a protrusion is the end facing away from the lid and towards the substrate, and the encapsulant has a generally flat surface and forms one or more elevations, wherein each of the one or more elevations encloses an upper end of a different one of the plurality of electronic or electrically conducting components, and encloses the lower end of a respective one of the one or more protrusions, wherein the upper end of an electronic or electrically conducting component is an end facing away from the substrate and towards the lid.

7. 发明公开

EP4270454A2 POWER SEMICONDUCTOR MODULE COMPRISING A FIRST AND A SECOND COMPARTMENT AND METHOD FOR FABRICATING THE SAME 审中-公开
公开(公告)号：EP4270454A2
公开(公告)日：2023-11-01
申请号：EP23168313.7
申请日：2023-04-17
申请人： Infineon Technologies AG
发明人： HARTUNG, Hans , GOLDAMMER, Martin , EHLERS, Carsten , ENGELKEMEIER, Katja , BOENIG, Guido
IPC分类号： H01L21/56 , H01L23/24 , H01L23/31 , H01L21/54 , H01L23/16
摘要： A power semiconductor module comprises: a power semiconductor die arranged on a power substrate, a housing enclosing the power semiconductor die and the power substrate, wherein an interior volume formed by the housing is divided by interior walls into at least a first compartment and a second compartment, wherein the power semiconductor die is arranged within the first compartment, a first encapsulation material encapsulating the power semiconductor die and at least partially filling the first compartment, and a second encapsulation material different from the first encapsulation material, the second encapsulation material encapsulating the first encapsulation material and at least partially filling the second compartment, wherein the first encapsulation material is arranged within the first compartment but not within the second compartment.

8. 发明公开

EP4270453A1 METHOD FOR FABRICATING A POWER SEMICONDUCTOR MODULE COMPRISING AN ENCAPSULATION MATERIAL WITH A HIGH THERMOSTABILITY AND POWER SEMICONDUCTOR MODULE 审中-公开
公开(公告)号：EP4270453A1
公开(公告)日：2023-11-01
申请号：EP22170459.6
申请日：2022-04-28
申请人： Infineon Technologies AG
发明人： GOLDAMMER, Martin , BOENIG, Guido , EHLERS, Carsten
IPC分类号： H01L21/56 , H01L23/24 , H01L23/31 , H01L21/54
摘要： A method for fabricating a power semiconductor module comprises: arranging a power semiconductor die on a power substrate, electrically connecting the power semiconductor die to the power substrate using an electrical connector, covering at least selective portions of the power semiconductor die and the electrical connector with a first encapsulation material, enclosing the power semiconductor die and the power substrate with a housing, and arranging a second encapsulation material on the first encapsulation material, such that the first and second encapsulation materials at least partially fill an interior volume formed by the housing, wherein the first encapsulation material exhibits a higher thermostability than the second encapsulation material.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式