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1. 发明公开

EP4270469A1 POWER SEMICONDUCTOR MODULE 审中-公开
公开(公告)号：EP4270469A1
公开(公告)日：2023-11-01
申请号：EP22170731.8
申请日：2022-04-29
申请人： Infineon Technologies AG
发明人： LUDWIG, Marco , GOLDAMMER, Martin
IPC分类号： H01L23/24 , H01L23/04
摘要： A power semiconductor module arrangement comprises a substrate comprising a dielectric insulation layer and a first metallization layer attached to the dielectric insulation layer, at least one semiconductor body arranged on the first metallization layer, a housing at least partly enclosing the substrate, the housing comprising a plurality of sidewalls and a lid, a casting compound formed of a first material and partly filling the housing, thereby covering the substrate and the at least one semiconductor body arranged thereon, a first element extending from the lid of the housing into the casting compound in a direction towards the substrate, and a detaining element arranged between the first element and at least one of the plurality of sidewalls of the housing, and configured to prevent traces of the first material wetting the lid of the housing from flowing along the lid from the first element to the one or more sidewalls.

2. 发明公开

EP4227986A1 POWER SEMICONDUCTOR MODULE ARRANGEMENT AND METHODS FOR PRODUCING A SEMICONDUCTOR ARRANGEMENT 审中-实审
公开(公告)号：EP4227986A1
公开(公告)日：2023-08-16
申请号：EP22156054.3
申请日：2022-02-10
申请人： Infineon Technologies AG
发明人： LASSMANN, Matthias , ARENS, Andre , BOENIG, Guido , LUDWIG, Marco
IPC分类号： H01L23/055 , H01L23/053 , H01L23/16 , H01L25/07
摘要： A power semiconductor module arrangement comprises a housing (7), a substrate (10) arranged inside the housing (7), a printed circuit board (81) arranged inside the housing (7) distant from and in parallel to the substrate (10), an encapsulant (5) at least partly filling the interior of the housing (7), thereby covering the substrate (10) and the printed circuit board (81), and a heat protective layer (52) arranged inside the housing (7) between the substrate (10) and the printed circuit board (81), and extending in a plane that is parallel to the substrate (10) and the printed circuit board (81), wherein a thermal resistance of the heat protective layer (52) is greater than a thermal resistance of the encapsulant (5).

3. 发明公开

EP4195893A1 HOUSING FOR A POWER SEMICONDUCTOR MODULE ARRANGEMENT 审中-实审
公开(公告)号：EP4195893A1
公开(公告)日：2023-06-14
申请号：EP21212681.7
申请日：2021-12-07
申请人： Infineon Technologies AG
发明人： HERBRANDT, Alexander , ARENS, Andre , BRAEUTIGAM, Philipp , LUDWIG, Marco
IPC分类号： H05K7/20 , H01L23/40 , F16B41/00
摘要： An arrangement comprises a housing and a printed circuit board arranged vertically above the housing, wherein the housing comprises sidewalls, at least one protrusion attached to the sidewalls and arranged on the outside of the housing at a lower end of the housing distant from the printed circuit board, wherein at least one first through hole is provided in the at least one protrusion, a plurality of holding devices, wherein each holding device is arranged inside a first through hole and/or between the printed circuit board and the first through hole, and a plurality of fastening elements configured to attach the housing to a heat sink or base plate, wherein each of the plurality of holding devices is configured to clamp a different one of the fastening elements such that the fastening elements are secured in defined positions, and to align each of the fastening elements with a different one of the first through holes, the printed circuit board comprises a plurality of second through holes, wherein each of the second through holes is arranged vertically above and aligned with a different one of the plurality of fastening elements, a diameter of each of the second through holes is less than the largest diameter of the respective fastening element, and when a defined force is exerted on the fastening elements, the fastening elements are configured to move vertically through the respective first through holes in a direction away from the printed circuit board.

4. 发明公开

EP4148789A1 POWER SEMICONDUCTOR MODULES 审中-公开
公开(公告)号：EP4148789A1
公开(公告)日：2023-03-15
申请号：EP21196284.0
申请日：2021-09-13
申请人： Infineon Technologies AG
发明人： LUDWIG, Marco , BÖNIG, Guido
IPC分类号： H01L25/07 , H01L23/049 , H01L25/18 , H01L23/04 , H01L23/34
摘要： A power semiconductor module arrangement comprises at least one substrate comprising a dielectric insulation layer and a first metallization layer attached to the dielectric insulation layer; at least one semiconductor body arranged on the first metallization layer; a housing at least partly enclosing the substrate, the housing comprising sidewalls; and at least one press-on pin, wherein each press-on pin is arranged either on the substrate or on one of the at least one semiconductor body and extends from the substrate or the respective semiconductor body in a vertical direction that is perpendicular to a top surface of the substrate, and each press-on pin is mechanically coupled to at least one sidewall of the housing by means of a bar, each bar extending horizontally between the respective press-on pin and sidewall, and parallel to the top surface of the substrate.

5. 发明公开

EP3913665A1 A POWER SEMICONDUCTOR MODULE AND A METHOD FOR PRODUCING A POWER SEMICONDUCTOR MODULE 审中-实审
公开(公告)号：EP3913665A1
公开(公告)日：2021-11-24
申请号：EP20175217.7
申请日：2020-05-18
申请人： Infineon Technologies AG
发明人： LUDWIG, Marco
IPC分类号： H01L23/40
摘要： A power semiconductor module comprises at least one semiconductor substrate (10) comprising a dielectric insulation layer (11) and a first metallization layer (111) attached to the dielectric insulation layer (11), at least one semiconductor body (20) arranged on the first metallization layer (111), at least one end stop element (48), wherein each end stop element (48) is arranged either on the semiconductor substrate (10) or on one of the at least one semiconductor body (20) and extends from the semiconductor substrate (10) or the respective semiconductor body (20) in a vertical direction (y) that is perpendicular to a top surface of the semiconductor substrate (10), and a housing at least partly enclosing the semiconductor substrate (10), the housing comprising sidewalls (42) and a cover (44). The housing further comprises at least one press-on pin (46), each of the at least one press-on pin extending from the cover (44) of the housing towards one of the at least one end stop element (48), and exerting a pressure on the respective end stop element (48).

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