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1. 发明公开

EP3185302A1 METHOD FOR MANUFACTURING A III-V GATE ALL AROUND SEMICONDUCTOR DEVICE 有权
标题翻译：在半导体器件周围制造III-V栅极的方法
公开(公告)号：EP3185302A1
公开(公告)日：2017-06-28
申请号：EP17154908.2
申请日：2015-03-25
申请人： IMEC vzw
发明人： Waldron, Niamh , Merckling, Clement , Collaert, Nadine
IPC分类号： H01L29/775 , H01L29/06 , H01L29/66 , H01L29/10 , B82Y10/00 , B82Y40/00 , H01L29/20
CPC分类号： H01L27/0886 , B82Y10/00 , B82Y40/00 , H01L21/02381 , H01L21/02538 , H01L21/02579 , H01L21/0262 , H01L21/02639 , H01L29/04 , H01L29/0649 , H01L29/0673 , H01L29/0676 , H01L29/1079 , H01L29/20 , H01L29/401 , H01L29/413 , H01L29/42392 , H01L29/66469 , H01L29/66545 , H01L29/6681 , H01L29/775 , H01L29/7853 , H01L29/78681 , H01L29/78696
摘要： A gate-all-around semiconductor device and a method for manufacturing a gate-all-around semiconductor device are disclosed. The gate-all-around (GAA) semiconductor device comprises a semiconductor substrate (100) comprising a first crystalline semiconductor material; two suspended nanowires (105a, 105b) horizontally adjacent at a distance D being located at least partially above and in between a pair of adjacent STI regions (101) and the two suspended nanowires being held in place by a source region (121) and a drain region (122) at both ends of the at least one suspended nanostructure, the two suspended nanowires comprising a third crystalline semiconductor material which is different from the first crystalline semiconductor material, wherein a cavity (114) is present between the suspended nanowires (105a, 105b), opposite sidewalls of the STI regions (101) and the semiconductor substrate (100), wherein the suspended nanowires are wrapped by a final gate stack and wherein the top surface and the sidewalls of the STI regions and the exposed surface of the semiconductor substrate from the cavity are also covered by the final gate stack and wherein distance D is larger than the thickness of the final gate stack and is smaller than the width of the cavity.
摘要翻译：公开了一种全环绕半导体器件和一种制造全环绕半导体器件的方法。全环栅（GAA）半导体器件包括：半导体衬底（100），其包括第一晶体半导体材料; 以距离D水平相邻的两个悬浮纳米线（105a，105b）至少部分地位于一对相邻STI区域（101）之上和之间，并且两个悬置纳米线由源极区域（121）和所述两个悬挂纳米线包括与所述第一晶体半导体材料不同的第三晶体半导体材料，其中空腔（114）存在于所述悬置纳米线（105a）之间，所述空腔（114）存在于所述悬置纳米线，所述STI区域（101）和所述半导体衬底（100）的相对侧壁，其中所述悬置纳米线由最终栅极叠层包裹，并且其中所述STI区域的顶表面和侧壁以及所述来自所述空腔的半导体衬底也被所述最终栅极叠层覆盖，并且其中距离D大于所述最终栅极叠层的厚度且小于所述空腔的宽度性。

2. 发明公开

EP2924738A1 METHOD FOR MANUFACTURING A III-V GATE ALL AROUND SEMICONDUCTOR DEVICE 有权
标题翻译：制造方法III-V GATE-全方位半导体器件
公开(公告)号：EP2924738A1
公开(公告)日：2015-09-30
申请号：EP15160743.9
申请日：2015-03-25
申请人： IMEC VZW
发明人： Waldron, Niamh , Merckling, Clement , Collaert, Nadine
IPC分类号： H01L29/775 , H01L29/66 , H01L29/06 , H01L29/10 , B82Y10/00 , B82Y40/00 , H01L29/20
CPC分类号： H01L27/0886 , B82Y10/00 , B82Y40/00 , H01L21/02381 , H01L21/02538 , H01L21/02579 , H01L21/0262 , H01L21/02639 , H01L29/04 , H01L29/0649 , H01L29/0673 , H01L29/0676 , H01L29/1079 , H01L29/20 , H01L29/401 , H01L29/413 , H01L29/42392 , H01L29/66469 , H01L29/66545 , H01L29/6681 , H01L29/775 , H01L29/7853 , H01L29/78681 , H01L29/78696
摘要： A gate-all-around semiconductor device and a method for manufacturing a gate-all-around (GAA) semiconductor device are disclosed. The method comprises providing on a semiconductor substrate (100) in between STI regions (101) at least one suspended nanostructure (105) anchored by a source (121) and a drain region (122), the suspended nanostructure comprising a crystalline semiconductor material which is different from the semiconductor substrate. A gate stack (117) is provided around the at least one suspended nanostructure.

3. 发明授权

EP3185302B1 GATE-ALL-AROUND SEMICONDUCTOR DEVICE WITH TWO GROUP III-V SEMICONDUCTOR NANOWIRES 有权
标题翻译：具有两个III-V族半导体纳米簇的栅极全能型半导体器件
公开(公告)号：EP3185302B1
公开(公告)日：2018-05-09
申请号：EP17154908.2
申请日：2015-03-25
申请人： IMEC vzw
发明人： Waldron, Niamh , Merckling, Clement , Collaert, Nadine
IPC分类号： H01L29/775 , H01L21/336 , H01L29/06 , H01L29/10 , B82Y10/00 , B82Y40/00 , H01L29/20 , H01L21/02 , H01L29/423
CPC分类号： H01L27/0886 , B82Y10/00 , B82Y40/00 , H01L21/02381 , H01L21/02538 , H01L21/02579 , H01L21/0262 , H01L21/02639 , H01L29/04 , H01L29/0649 , H01L29/0673 , H01L29/0676 , H01L29/1079 , H01L29/20 , H01L29/401 , H01L29/413 , H01L29/42392 , H01L29/66469 , H01L29/66545 , H01L29/6681 , H01L29/775 , H01L29/7853 , H01L29/78681 , H01L29/78696
摘要： A gate-all-around semiconductor device and a method for manufacturing a gate-all-around (GAA) semiconductor device are disclosed. The method comprises providing on a semiconductor substrate (100) in between STI regions (101) at least one suspended nanostructure (105) anchored by a source (121) and a drain region (122), the suspended nanostructure comprising a crystalline semiconductor material which is different from the semiconductor substrate. A gate stack (117) is provided around the at least one suspended nanostructure.

4. 发明授权

EP2924738B1 METHOD FOR MANUFACTURING A III-V GATE ALL AROUND SEMICONDUCTOR DEVICE 有权
标题翻译： VERFAHREN ZUR HERSTELLUNG EINER III-V GATE-RUNDUM-HALBLEITERVORRICHTUNG
公开(公告)号：EP2924738B1
公开(公告)日：2017-03-22
申请号：EP15160743.9
申请日：2015-03-25
申请人： IMEC VZW
发明人： Waldron, Niamh , Merckling, Clement , Collaert, Nadine
IPC分类号： H01L29/775 , H01L29/40 , H01L29/06 , H01L29/66 , H01L29/20 , H01L29/10 , B82Y10/00 , B82Y40/00
CPC分类号： H01L27/0886 , B82Y10/00 , B82Y40/00 , H01L21/02381 , H01L21/02538 , H01L21/02579 , H01L21/0262 , H01L21/02639 , H01L29/04 , H01L29/0649 , H01L29/0673 , H01L29/0676 , H01L29/1079 , H01L29/20 , H01L29/401 , H01L29/413 , H01L29/42392 , H01L29/66469 , H01L29/66545 , H01L29/6681 , H01L29/775 , H01L29/7853 , H01L29/78681 , H01L29/78696
摘要： A gate-all-around semiconductor device and a method for manufacturing a gate-all-around (GAA) semiconductor device are disclosed. The method comprises providing on a semiconductor substrate (100) in between STI regions (101) at least one suspended nanostructure (105) anchored by a source (121) and a drain region (122), the suspended nanostructure comprising a crystalline semiconductor material which is different from the semiconductor substrate. A gate stack (117) is provided around the at least one suspended nanostructure.
摘要翻译：公开了一种全栅半导体器件及其制造方法。该方法包括在STI区域（101）之间的半导体衬底（100）上提供由源（121）和漏区（122）锚定的至少一个悬浮纳米结构（105），所述悬浮纳米结构包括晶体半导体材料，其结晶半导体材料与半导体衬底不同。在所述至少一个悬浮的纳米结构周围设置栅极堆叠（117）。

5. 发明公开

EP2924722A1 Method for manufacturing a semiconductor-on-insulator device 审中-公开
标题翻译： VERFAHREN ZUR HERSTELLUNG EINER HALBLEITER-AUF-ISOLATOR-VORRICHTUNG
公开(公告)号：EP2924722A1
公开(公告)日：2015-09-30
申请号：EP15160738.9
申请日：2015-03-25
申请人： IMEC VZW
发明人： Waldron, Niamh
IPC分类号： H01L21/762
CPC分类号： H01L21/76254 , H01L21/76224 , H01L21/8252 , H01L21/84 , H01L21/845 , H01L27/0605
摘要： A method for manufacturing semiconductor-on-insulator devices is disclosed. The method comprises providing a pre-patterned donor wafer, providing a handling wafer and bonding the pre-patterned donor wafer to the handling wafer by contacting the first oxide layer to the handling wafer. Providing a pre-patterned donor wafer comprises providing a donor substrate comprising a first semiconductor material; forming shallow trench isolation (STI) regions in the donor substrate; forming fins in the donor substrate in between the STI regions, the fins comprising a Group III-V or Group IV semiconductor material (different from the first semiconducting material), the fins extending from the donor substrate in between the STI regions; providing an first oxide layer overlying the STI regions and the fins. After bonding the donor wafer to the handling wafer at least part of the first semiconducting material of the pre-patterned donor wafer is removed and the STI regions and the fins are thinned thereby forming channel regions comprising the Group III-V or Group IV semiconductor material.
摘要翻译：公开了一种用于制造绝缘体上半导体器件的方法。该方法包括提供预先构图的施主晶片，提供处理晶片，并通过使第一氧化物层与处理晶片接触来将预构图的施主晶片接合到处理晶片。提供预构图的施主晶片包括提供包括第一半导体材料的施主衬底; 在供体衬底中形成浅沟槽隔离（STI）区域; 在所述STI区域之间的所述施主衬底中形成翅片，所述鳍片包括III-V族或IV族半导体材料（不同于所述第一半导体材料），所述鳍片从所述施主衬底延伸在所述STI区域之间; 提供覆盖STI区域和鳍片的第一氧化物层。在将施主晶片结合到处理晶片之后，去除预图案化施主晶片的至少一部分第一半导体材料，并且STI区域和鳍片变薄，从而形成包括III-V族或IV族半导体材料的沟道区。

6. 发明公开

EP2849219A1 Method for manufacturing transistors and associated substrate 审中-公开
标题翻译： Verfahren zur Herstellung von Transistoren undzugehörigesSubstrat
公开(公告)号：EP2849219A1
公开(公告)日：2015-03-18
申请号：EP13183985.4
申请日：2013-09-11
申请人： IMEC VZW
发明人： Waldron, Niamh , Witters, Liesbeth
IPC分类号： H01L21/8258 , H01L21/8238 , H01L27/092 , H01L29/66 , H01L29/04
CPC分类号： H01L27/0922 , H01L21/762 , H01L21/823807 , H01L21/823821 , H01L21/823878 , H01L21/8258 , H01L27/0924 , H01L29/045 , H01L29/0653 , H01L29/161 , H01L29/20 , H01L29/267
摘要： A method for manufacturing a CMOS device, comprising providing a starting substrate, the starting substrate comprising a silicon substrate the surface of which is oriented along the (100) crystal plane;
- forming shallow trench isolation structures in a first predetermined region, thereby defining channel areas in said substrate embodied as silicon protrusions extending from said silicon substrate and being isolated from each other by means of isolation structures;
- removing said silicon protrusions, thereby creating trenches;
- filling said trenches by epitaxially growing a III-V material in said trenches, to thereby form channel structures of transistors of a first type which are essentially defect-free; and associated substrate.
摘要翻译：一种制造CMOS器件的方法，包括提供起始衬底，所述起始衬底包括硅衬底，所述衬底的表面沿（100）晶面定向; - 在第一预定区域中形成浅沟槽隔离结构，从而限定所述衬底中的通道区域，其被实施为从所述硅衬底延伸并通过隔离结构彼此隔离的硅突起; - 去除所述硅突起，从而产生沟槽; - 通过在所述沟槽中外延生长III-V材料来填充所述沟槽，从而形成基本上无缺陷的第一类晶体管的沟道结构; 和相关底物。

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