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1. 发明公开

EP3276654A1 NON-VOLATILE SRAM MEMORY CELL AND NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE 审中-公开
标题翻译：非易失性SRAM存储器单元和非易失性半导体存储器件
公开(公告)号：EP3276654A1
公开(公告)日：2018-01-31
申请号：EP16772411.1
申请日：2016-03-18
申请人： Floadia Corporation
发明人： SHINAGAWA Yutaka , TANIGUCHI Yasuhiro , KASAI Hideo , SAKURAI Ryotaro , KAWASHIMA Yasuhiko , TOYA Tatsuro , OKUYAMA Kosuke
IPC分类号： H01L21/8244 , G11C14/00 , H01L21/336 , H01L21/8247 , H01L27/11 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/1104 , G11C11/412 , G11C14/0063 , G11C16/0425 , H01L27/105 , H01L27/1116 , H01L27/11568 , H01L27/11573 , H01L29/788 , H01L29/792
摘要： A non-volatile SRAM memory cell and a non-volatile semiconductor memory device capable of programming SRAM data in a SRAM (15) to a non-volatile memory unit (16) through fast operation of the SRAM (15) are disclosed. A non-volatile semiconductor memory device (1) can achieve reduction in a voltage necessary for a programming operation to program SRAM data to the non-volatile memory unit (16). Thus, a first access transistor (21 a), a second access transistor (21 b), a first load transistor (22a), a second load transistor (22b), a first drive transistor (23a), and a second drive transistor (23b) included in the SRAM (15) connected with the non-volatile memory unit (16) can each include a gate insulating film having a thickness less than or equal to 4 nm, which achieves fast operation of the SRAM (15) at a lower power supply voltage.
摘要翻译：公开了一种能够通过SRAM（15）的快速操作将SRAM中的SRAM数据编程到非易失性存储器单元（16）的非易失性SRAM存储器单元和非易失性半导体存储器件。非易失性半导体存储器件（1）可以实现编程操作所需的电压的降低，以将SRAM数据编程到非易失性存储器单元（16）。因此，第一存取晶体管（21a），第二存取晶体管（21b），第一负载晶体管（22a），第二负载晶体管（22b），第一驱动晶体管（23a）和第二驱动晶体管（ 23b）包括在与非易失性存储单元（16）连接的SRAM（15）中的每一个都可以包括具有小于或等于4nm的厚度的栅极绝缘膜，其实现SRAM（15）在降低电源电压。

2. 发明公开

EP3232465A1 MEMORY CELL AND NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE 有权
标题翻译：存储器单元和非易失性半导体存储器件
公开(公告)号：EP3232465A1
公开(公告)日：2017-10-18
申请号：EP15851362.2
申请日：2015-10-06
申请人： Floadia Corporation
发明人： SHINAGAWA Yutaka , TANIGUCHI Yasuhiro , KASAI Hideo , SAKURAI Ryotaro , KAWASHIMA Yasuhiko , TOYA Tatsuro , OKUYAMA Kosuke
IPC分类号： H01L21/336 , G11C16/02 , G11C16/04 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L29/788 , G11C11/34 , G11C16/0425 , G11C16/0433 , G11C16/08 , H01L27/115 , H01L28/00 , H01L29/792 , H01L45/04
摘要： A voltage applied to a bit line (BL1) or a voltage applied to a source line (SL) is reduced to a value that allows a first select gate structure (5) or a second select gate structure (6) to block electrical connection between the bit line (BL1) and a channel layer (CH) or between the source line (SL) and the channel layer (CH), irrespective of a charge storage gate voltage needed to inject charge into a charge storage layer (EC) by a quantum tunneling effect. In accordance with the reduction in voltage(s) applied to the bit line (BL1) and the source line (SL), thickness of a first select gate insulating film (30) of the first select gate structure (5) and thickness of a second select gate insulating film (33) of the second select gate structure (6) are reduced. High-speed operation is achieved correspondingly. In accordance with the reduction in voltage(s) applied to the bit line (BL1) and the source line (SL), thickness of a gate insulating film of a field effect transistor in a peripheral circuit that controls a memory cell is reduced. The area of the peripheral circuit is reduced correspondingly.
摘要翻译：施加到位线（BL1）的电压或施加到源极线（SL）的电压降低到允许第一选择栅极结构（5）或第二选择栅极结构（6）阻止位线（BL1）和沟道层（CH）之间或源极线（SL）和沟道层（CH）之间的电荷存储栅极电压，而不考虑将电荷注入电荷存储层量子隧道效应。根据施加到位线（BL1）和源极线（SL）的电压的减少，第一选择栅极结构（5）的第一选择栅极绝缘膜（30）的厚度和减少第二选择栅极结构（6）的第二选择栅极绝缘膜（33）。高速运转也相应实现。根据施加到位线（BL1）和源极线（SL）的电压的减少，控制存储器单元的外围电路中的场效应晶体管的栅极绝缘膜的厚度减小。外围电路的面积相应减小。

3. 发明授权

EP3214649B1 ANTI-FUSE MEMORY AND SEMICONDUCTOR STORAGE DEVICE 有权转让
公开(公告)号：EP3214649B1
公开(公告)日：2020-03-11
申请号：EP15855744.7
申请日：2015-10-09
申请人： Floadia Corporation
发明人： TANIGUCHI Yasuhiro , KASAI Hideo , KAWASHIMA Yasuhiko , SAKURAI Ryotaro , SHINAGAWA Yutaka , OKUYAMA Kosuke
IPC分类号： H01L27/10 , G11C16/02 , G11C16/06 , G11C17/06 , G11C17/16 , G11C17/18 , H01L23/525 , H01L27/112 , H01L27/115

4. 发明公开

EP3293756A1 MEMORY CELL, NONVOLATILE SEMICONDUCTOR STORAGE DEVICE, AND METHOD FOR MANUFACTURING NONVOLATILE SEMICONDUCTOR STORAGE DEVICE 有权
标题翻译：存储器单元，非易失性半导体存储装置以及制造非易失性半导体存储装置的方法
公开(公告)号：EP3293756A1
公开(公告)日：2018-03-14
申请号：EP16875485.1
申请日：2016-12-07
申请人： Floadia Corporation
发明人： OKADA Daisuke , YANAGISAWA Kazumasa , OWADA Fukuo , YOSHIDA Shoji , KAWASHIMA Yasuhiko , YOSHIDA Shinji , TANIGUCHI Yasuhiro , OKUYAMA Kosuke
IPC分类号： H01L21/336 , G11C16/02 , G11C16/04 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11521 , G11C16/04 , G11C16/0433 , G11C16/10 , H01L27/11519 , H01L27/11565 , H01L27/11568 , H01L29/42344 , H01L29/66545 , H01L29/6681 , H01L29/785 , H01L29/788 , H01L29/792
摘要： When a memory cell (MC) is downsized by reducing the distance between a drain region (12a) and a source region (12b) on the surface of a fin (S2) with a high impurity concentration inside the fin (S2), the shape of the fin (S2) can be set such that a potential difference between a memory gate electrode (MG) and the fin (S2) is reduced to suppress the occurrence of disturbance. Accordingly, the memory cell (MC) achieves downsizing and suppression of the occurrence of disturbance.
摘要翻译：当通过减小在鳍片（S2）内具有高杂质浓度的鳍片（S2）的表面上的漏极区域（12a）和源极区域（12b）之间的距离来缩小存储器单元（MC）（S2）的位置可以被设置为使得存储器栅极电极（MG）和鳍片（S2）之间的电位差减小以抑制干扰的发生。因此，存储单元（MC）实现了小型化和抑制干扰的发生。

5. 发明公开

EP3300103A1 MEMORY CELL AND NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE 有权
标题翻译：存储器单元和非易失性半导体存储器件
公开(公告)号：EP3300103A1
公开(公告)日：2018-03-28
申请号：EP16803262.1
申请日：2016-05-27
申请人： Floadia Corporation
发明人： TANIGUCHI Yasuhiro , OWADA Fukuo , KAWASHIMA Yasuhiko , YOSHIDA Shinji , OKUYAMA Kosuke
IPC分类号： H01L21/8247 , H01L21/336 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L29/408 , G11C16/0466 , G11C16/10 , G11C16/26 , H01L27/115 , H01L27/11568 , H01L29/401 , H01L29/42344 , H01L29/66833 , H01L29/788 , H01L29/792
摘要： A memory cell and a non-volatile semiconductor memory device are disclosed. Nitride sidewall layers (32a and 32b) are respectively disposed in a first sidewall spacer (28a) and a second sidewall spacer (28b), to separate a memory gate electrode (MG) and a first select gate electrode (DG) from each other and the memory gate electrode (MG) and a second select gate electrode (SG) from each other. Hence, a breakdown voltage is improved around the memory gate electrode (MG) as compared with a conventional case in which the first sidewall spacer (28a) and the second sidewall spacer (28b) are simply made of insulating oxide films. The nitride sidewall layers (32a and 32b) are disposed farther from a memory well (MW) than a charge storage layer (EC). Hence, charge is unlikely to be injected into the nitride sidewall layers (32a and 32b) at charge injection from the memory well (MW) into the charge storage layer (EC), thereby preventing an operation failure due to charge storage in a region other than the charge storage layer (EC).
摘要翻译：公开了一种存储单元和非易失性半导体存储器件。氮化物侧壁层（32a和32b）分别设置在第一侧壁间隔物（28a）和第二侧壁间隔物（28b）中，以将存储器栅极电极（MG）和第一选择栅极电极（DG）彼此分隔开并且存储器栅极电极（MG）和第二选择栅极电极（SG）。因此，与其中第一侧壁间隔物（28a）和第二侧壁间隔物（28b）仅由绝缘氧化物膜制成的传统情况相比，存储器栅极电极（MG）周围的击穿电压得到改善。氮化物侧壁层（32a和32b）比电荷存储层（EC）更远离存储阱（MW）设置。因此，在从存储器阱（MW）向电荷存储层（EC）注入电荷时，电荷不可能注入到氮化物侧壁层（32a和32b）中，由此防止由于其他区域中的电荷存储而导致的操作故障比电荷存储层（EC）。

6. 发明公开

EP3316282A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE PRODUCTION METHOD, AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 有权
标题翻译：半导体集成电路器件制造方法和半导体集成电路器件
公开(公告)号：EP3316282A1
公开(公告)日：2018-05-02
申请号：EP16834972.8
申请日：2016-07-26
申请人： Floadia Corporation
发明人： OWADA Fukuo , TANIGUCHI Yasuhiro , KAWASHIMA Yasuhiko , YOSHIDA Shinji , KASAI Hideo , SAKURAI Ryotaro , SHINAGAWA Yutaka , OKUYAMA Kosuke
IPC分类号： H01L21/336 , H01L21/8234 , H01L27/088 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L29/792 , H01L21/823456 , H01L27/092 , H01L27/11565 , H01L27/11573 , H01L29/42344
摘要： A method for producing semiconductor integrated circuit devices and a semiconductor integrated circuit device produced by the method are provided. In the method, when a first select gate electrode (G2a, G2b) and a second select gate electrode (G3a, G3b) that are independently controllable are formed in a production process, an extra dedicated photomask process for electrically separating the first select gate electrode (G2a, G2b) and the second select gate electrode (G3a, G3b) is not needed in addition to a conventional dedicated photomask process of fabricating a memory circuit region only, thereby achieving reduction in a production cost accordingly.
摘要翻译：提供了一种用于制造半导体集成电路器件的方法以及由该方法制造的半导体集成电路器件。在该方法中，当在制造工艺中形成可独立控制的第一选择栅极电极（G2a，G2b）和第二选择栅极电极（G3a，G3b）时，用于电分离第一选择栅极电极的额外专用光掩模工艺（G2a，G2b）和第二选择栅极电极（G3a，G3b），除了仅制造存储器电路区域的传统专用光掩模工艺之外，因此实现了生产成本的降低。

7. 发明公开

EP3208831A1 METHOD FOR PRODUCING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICES, AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 有权
标题翻译：制造半导体集成电路器件的方法和半导体集成电路器件
公开(公告)号：EP3208831A1
公开(公告)日：2017-08-23
申请号：EP15850113.0
申请日：2015-10-06
申请人： Floadia Corporation
发明人： TANIGUCHI Yasuhiro , KAWASHIMA Yasuhiko , KASAI Hideo , SAKURAI Ryotaro , SHINAGAWA Yutaka , OKUYAMA Kosuke
IPC分类号： H01L21/336 , H01L21/8234 , H01L27/088 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L29/792 , H01L21/823456 , H01L27/088 , H01L27/11565 , H01L27/11573 , H01L29/42344
摘要： A method for producing a semiconductor integrated circuit device, and a semiconductor integrated circuit device are disclosed. In the method, a first select gate electrode (G2a, G2b) and a second select gate electrode (G3a, G3b) electrically insulated from each other are formed in a memory circuit region (ER1) through a photomask process of forming a logic gate electrode (G5, G6) in a peripheral circuit region (ER2). Thus, even when the first select gate electrode (G2a or G2b) and the second select gate electrode (G3a, G3b) are formed to be separately controllable, an extra dedicated photomask process of fabricating only the memory circuit region (ER1) does not need to be performed in addition to a conventional dedicated photomask process of fabricating only a memory circuit region. Thereby, production cost is reduced accordingly.
摘要翻译：公开了一种制造半导体集成电路器件的方法和半导体集成电路器件。在该方法中，通过形成逻辑栅电极的光掩模工艺在存储电路区域（ER1）中形成彼此电绝缘的第一选择栅电极（G2a，G2b）和第二选择栅电极（G3a，G3b）（G5，G6）在外围电路区域（ER2）中。因此，即使当第一选择栅极电极（G2a或G2b）和第二选择栅极电极（G3a，G3b）形成为可单独控制时，仅制造存储器电路区域（ER1）的额外专用光掩模工艺也不需要除了仅制造存储器电路区域的常规专用光掩模工艺之外，还要执行该工艺。由此，生产成本相应降低。

8. 发明公开

EP2911190A1 NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE 有权转让
标题翻译：非易失性半导体存储装置
公开(公告)号：EP2911190A1
公开(公告)日：2015-08-26
申请号：EP13847756.7
申请日：2013-09-27
申请人： Floadia Corporation
发明人： TANIGUCHI Yasuhiro , KASAI Hideo , SHINAGAWA Yutaka , OKUYAMA Kosuke
IPC分类号： H01L21/8247 , G11C16/04 , H01L21/336 , H01L21/8244 , H01L27/11 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G11C14/0063 , G11C7/18 , G11C8/16 , G11C16/04 , G11C16/0441 , G11C16/08 , G11C16/12 , G11C16/14 , G11C16/24 , G11C16/26 , H01L27/11519 , H01L27/11558 , H01L29/7881
摘要： Provided is a non-volatile semiconductor storage device that can surely prevent malfunction of read transistors without an increase in the number of bit lines. In a non-volatile semiconductor storage device (1), a second bit line (BLN1) that is connected to a program transistor (5a) of a first cell (2a) so as to serve for data writing is caused to double as a bit line for reading in another second cell (2b) by switching switch transistors (SWa, SWb), and program transistors (5a, 5b) and erase transistors (3a, 3b) that serve as charge transfer paths at the time of writing data and at the time of deletion of data are provided. This configuration makes it possible to surely prevent malfunction of read transistors (4a, 4b) that occurs when the read transistors are used for writing or deletion of data, without increasing the number of bit lines.
摘要翻译：提供了一种非易失性半导体存储装置，其能够可靠地防止读取晶体管的故障而不增加位线的数量。在非易失性半导体存储器件（1）中，连接到第一单元（2a）的编程晶体管（5a）以用于数据写入的第二位线（BLN1）被加倍为一位通过在写入数据时切换开关晶体管（SWa，SWb）和用作电荷传输路径的编程晶体管（5a，5b）和擦除晶体管（3a，3b）以及在另一个第二单元提供删除数据的时间。这种配置使得可以确实地防止在读取晶体管用于写入或删除数据时发生的读取晶体管（4a，4b）的故障，而不增加位线的数量。

9. 发明公开

EP3291292A1 MEMORY CELL, SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 有权
标题翻译：存储器单元，半导体集成电路装置及制造半导体集成电路装置的方法
公开(公告)号：EP3291292A1
公开(公告)日：2018-03-07
申请号：EP16789528.3
申请日：2016-04-26
申请人： Floadia Corporation
发明人： OWADA Fukuo , KAWASHIMA Yasuhiko , YOSHIDA Shinji , TANIGUCHI Yasuhiro , OKUYAMA Kosuke
IPC分类号： H01L21/8247 , H01L21/336 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L29/792 , G11C16/0425 , G11C16/0466 , H01L21/28282 , H01L27/11573 , H01L29/42344 , H01L29/66833
摘要： A semiconductor integrated circuit device, and a method for manufacturing a semiconductor integrated circuit device are disclosed. A first select gate electrode (DG) and a second select gate electrode (SG) are sidewall-shaped along sidewalls of a memory gate structure (4). With this configuration, the memory gate structure (4) is not disposed on the first select gate electrode (DG) and the second select gate electrode (SG). Accordingly, the memory gate structure (4), the first select gate structure (5), and the second select gate structure (6) can have equal heights, thereby achieving reduction in size as compared to a conventional case. In addition, a silicide layer (S1) on the first select gate electrode (DG) and a silicide layer (S2) on the second select gate electrode (SG) can be separated farther from a memory gate electrode (MG) by the thickness of a cap film (CP1). Accordingly, the silicide layers (S1 and S2) on the first select gate electrode (DG) and the second select gate electrode (SG) are unlikely to contact with the memory gate electrode (MG), thereby preventing a short-circuit defect of the memory gate electrode (MG).
摘要翻译：公开了一种半导体集成电路器件以及一种用于制造半导体集成电路器件的方法。第一选择栅极电极（DG）和第二选择栅极电极（SG）沿存储器栅极结构（4）的侧壁成侧壁形状。利用该配置，存储栅极结构（4）不被布置在第一选择栅极电极（DG）和第二选择栅极电极（SG）上。因此，与常规情况相比，存储栅极结构（4），第一选择栅极结构（5）和第二选择栅极结构（6）可具有相同的高度，从而实现尺寸的减小。此外，第一选择栅极电极（DG）上的硅化物层（S1）和第二选择栅极电极（SG）上的硅化物层（S2）可以远离存储器栅极电极（MG）分开厚度一个盖膜（CP1）。因此，第一选择栅极电极（DG）和第二选择栅极电极（SG）上的硅化物层（S1和S2）不可能与存储器栅极电极（MG）接触，由此防止存储器栅电极（MG）。

10. 发明公开

EP3264464A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：EP3264464A1
公开(公告)日：2018-01-03
申请号：EP16755350.2
申请日：2016-02-19
申请人： Floadia Corporation
发明人： KASAI Hideo , TANIGUCHI Yasuhiro , KAWASHIMA Yasuhiko , SAKURAI Ryotaro , SHINAGAWA Yutaka , TOYA Tatsuro , YAMAGUCHI Takanori , OWADA Fukuo , YOSHIDA Shinji , HATADA Teruo , NODA Satoshi , KATO Takafumi , MURAYA Tetsuya , OKUYAMA Kosuke
IPC分类号： H01L27/10
CPC分类号： H01L27/11206 , G11C17/16 , H01L23/5252
摘要： In a semiconductor memory device (1), voltage application from a memory gate electrode (G) of the memory capacitor (4) to a word line can be blocked by a rectifier element (3) depending on values of voltages applied to the memory gate electrode (G) and the word line without using a conventional control circuit. The configuration eliminates the need to provide a switch transistor and a switch control circuit for turning on and off the switch transistor as in conventional cases, and accordingly achieves downsizing. In the semiconductor memory device (1), for example, each bit line contact (BC15) is shared by four anti-fuse memories (2a 6 , 2a 7 , 2a 10 , and 2a 11 ) adjacent to each other and each word line contact (WC12) is shared by four anti-fuse memories (2a 3 , 2a 4 , 2a 7 , and 2a 8 ) adjacent to each other, thereby achieving downsizing of the entire device as compared to a case in which the bit line contact and the word line contact are individually provided to each anti-fuse memory.
摘要翻译：在半导体存储器件（1）中，从存储电容器（4）的存储器栅电极（G）到字线的电压施加可以由整流器元件（3）根据施加到存储器栅极电极（G）和字线而不使用传统的控制电路。该配置消除了与传统情况中一样提供用于导通和关断开关晶体管的开关晶体管和开关控制电路的需要，并且相应地实现了小型化。在半导体存储器件（1）中，例如，每个位线触点（BC15）由彼此相邻的四个反熔丝存储器（2a6,2a7,2a10和2a11）共享，并且每个字线触点（WC12）是由彼此相邻的四个反熔丝存储器（2a3,2a4,2a7和2a8）共享，从而与其中位线接触件和字线接触件分别提供给每个反熔丝存储件的情况相比，由此实现了整个设备的小型化反熔丝内存。

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