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1. 发明公开

EP3264464A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：EP3264464A1
公开(公告)日：2018-01-03
申请号：EP16755350.2
申请日：2016-02-19
申请人： Floadia Corporation
发明人： KASAI Hideo , TANIGUCHI Yasuhiro , KAWASHIMA Yasuhiko , SAKURAI Ryotaro , SHINAGAWA Yutaka , TOYA Tatsuro , YAMAGUCHI Takanori , OWADA Fukuo , YOSHIDA Shinji , HATADA Teruo , NODA Satoshi , KATO Takafumi , MURAYA Tetsuya , OKUYAMA Kosuke
IPC分类号： H01L27/10
CPC分类号： H01L27/11206 , G11C17/16 , H01L23/5252
摘要： In a semiconductor memory device (1), voltage application from a memory gate electrode (G) of the memory capacitor (4) to a word line can be blocked by a rectifier element (3) depending on values of voltages applied to the memory gate electrode (G) and the word line without using a conventional control circuit. The configuration eliminates the need to provide a switch transistor and a switch control circuit for turning on and off the switch transistor as in conventional cases, and accordingly achieves downsizing. In the semiconductor memory device (1), for example, each bit line contact (BC15) is shared by four anti-fuse memories (2a 6 , 2a 7 , 2a 10 , and 2a 11 ) adjacent to each other and each word line contact (WC12) is shared by four anti-fuse memories (2a 3 , 2a 4 , 2a 7 , and 2a 8 ) adjacent to each other, thereby achieving downsizing of the entire device as compared to a case in which the bit line contact and the word line contact are individually provided to each anti-fuse memory.
摘要翻译：在半导体存储器件（1）中，从存储电容器（4）的存储器栅电极（G）到字线的电压施加可以由整流器元件（3）根据施加到存储器栅极电极（G）和字线而不使用传统的控制电路。该配置消除了与传统情况中一样提供用于导通和关断开关晶体管的开关晶体管和开关控制电路的需要，并且相应地实现了小型化。在半导体存储器件（1）中，例如，每个位线触点（BC15）由彼此相邻的四个反熔丝存储器（2a6,2a7,2a10和2a11）共享，并且每个字线触点（WC12）是由彼此相邻的四个反熔丝存储器（2a3,2a4,2a7和2a8）共享，从而与其中位线接触件和字线接触件分别提供给每个反熔丝存储件的情况相比，由此实现了整个设备的小型化反熔丝内存。

2. 发明公开

EP3276654A1 NON-VOLATILE SRAM MEMORY CELL AND NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE 审中-公开
标题翻译：非易失性SRAM存储器单元和非易失性半导体存储器件
公开(公告)号：EP3276654A1
公开(公告)日：2018-01-31
申请号：EP16772411.1
申请日：2016-03-18
申请人： Floadia Corporation
发明人： SHINAGAWA Yutaka , TANIGUCHI Yasuhiro , KASAI Hideo , SAKURAI Ryotaro , KAWASHIMA Yasuhiko , TOYA Tatsuro , OKUYAMA Kosuke
IPC分类号： H01L21/8244 , G11C14/00 , H01L21/336 , H01L21/8247 , H01L27/11 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/1104 , G11C11/412 , G11C14/0063 , G11C16/0425 , H01L27/105 , H01L27/1116 , H01L27/11568 , H01L27/11573 , H01L29/788 , H01L29/792
摘要： A non-volatile SRAM memory cell and a non-volatile semiconductor memory device capable of programming SRAM data in a SRAM (15) to a non-volatile memory unit (16) through fast operation of the SRAM (15) are disclosed. A non-volatile semiconductor memory device (1) can achieve reduction in a voltage necessary for a programming operation to program SRAM data to the non-volatile memory unit (16). Thus, a first access transistor (21 a), a second access transistor (21 b), a first load transistor (22a), a second load transistor (22b), a first drive transistor (23a), and a second drive transistor (23b) included in the SRAM (15) connected with the non-volatile memory unit (16) can each include a gate insulating film having a thickness less than or equal to 4 nm, which achieves fast operation of the SRAM (15) at a lower power supply voltage.
摘要翻译：公开了一种能够通过SRAM（15）的快速操作将SRAM中的SRAM数据编程到非易失性存储器单元（16）的非易失性SRAM存储器单元和非易失性半导体存储器件。非易失性半导体存储器件（1）可以实现编程操作所需的电压的降低，以将SRAM数据编程到非易失性存储器单元（16）。因此，第一存取晶体管（21a），第二存取晶体管（21b），第一负载晶体管（22a），第二负载晶体管（22b），第一驱动晶体管（23a）和第二驱动晶体管（ 23b）包括在与非易失性存储单元（16）连接的SRAM（15）中的每一个都可以包括具有小于或等于4nm的厚度的栅极绝缘膜，其实现SRAM（15）在降低电源电压。

3. 发明公开

EP3232465A1 MEMORY CELL AND NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE 有权
标题翻译：存储器单元和非易失性半导体存储器件
公开(公告)号：EP3232465A1
公开(公告)日：2017-10-18
申请号：EP15851362.2
申请日：2015-10-06
申请人： Floadia Corporation
发明人： SHINAGAWA Yutaka , TANIGUCHI Yasuhiro , KASAI Hideo , SAKURAI Ryotaro , KAWASHIMA Yasuhiko , TOYA Tatsuro , OKUYAMA Kosuke
IPC分类号： H01L21/336 , G11C16/02 , G11C16/04 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L29/788 , G11C11/34 , G11C16/0425 , G11C16/0433 , G11C16/08 , H01L27/115 , H01L28/00 , H01L29/792 , H01L45/04
摘要： A voltage applied to a bit line (BL1) or a voltage applied to a source line (SL) is reduced to a value that allows a first select gate structure (5) or a second select gate structure (6) to block electrical connection between the bit line (BL1) and a channel layer (CH) or between the source line (SL) and the channel layer (CH), irrespective of a charge storage gate voltage needed to inject charge into a charge storage layer (EC) by a quantum tunneling effect. In accordance with the reduction in voltage(s) applied to the bit line (BL1) and the source line (SL), thickness of a first select gate insulating film (30) of the first select gate structure (5) and thickness of a second select gate insulating film (33) of the second select gate structure (6) are reduced. High-speed operation is achieved correspondingly. In accordance with the reduction in voltage(s) applied to the bit line (BL1) and the source line (SL), thickness of a gate insulating film of a field effect transistor in a peripheral circuit that controls a memory cell is reduced. The area of the peripheral circuit is reduced correspondingly.
摘要翻译：施加到位线（BL1）的电压或施加到源极线（SL）的电压降低到允许第一选择栅极结构（5）或第二选择栅极结构（6）阻止位线（BL1）和沟道层（CH）之间或源极线（SL）和沟道层（CH）之间的电荷存储栅极电压，而不考虑将电荷注入电荷存储层量子隧道效应。根据施加到位线（BL1）和源极线（SL）的电压的减少，第一选择栅极结构（5）的第一选择栅极绝缘膜（30）的厚度和减少第二选择栅极结构（6）的第二选择栅极绝缘膜（33）。高速运转也相应实现。根据施加到位线（BL1）和源极线（SL）的电压的减少，控制存储器单元的外围电路中的场效应晶体管的栅极绝缘膜的厚度减小。外围电路的面积相应减小。

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