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1. 发明公开

EP4009380A2 CONTROLLED ION IMPLANTATION INTO SILICON CARBIDE 审中-公开
公开(公告)号：EP4009380A2
公开(公告)日：2022-06-08
申请号：EP21208162.4
申请日：2014-07-25
申请人： Cree, Inc.
发明人： SUVOROV, Alexander V. , PALA, Vipindas
IPC分类号： H01L29/78 , H01L29/08 , H01L29/10
摘要： Methods of forming a semiconductor structure include the use of channeled implants into silicon carbide crystals. Some methods include providing a silicon carbide layer having a crystallographic axis, heating the silicon carbide layer to a temperature of about 300 °C or more, implanting dopant ions into the heated silicon carbide layer at an implant angle between a direction of implantation and the crystallographic axis of less than about 2°, and annealing the silicon carbide layer at a time-temperature product of less than about 30,000 °C-hours to activate the implanted ions.

2. 发明公开

EP3940793A1 SUPERJUNCTION POWER SILICON CARBIDE SEMICONDUCTOR DEVICES FORMED VIA ION IMPLANTATION CHANNELING TECHNIQUES AND RELATED METHODS 审中-公开
公开(公告)号：EP3940793A1
公开(公告)日：2022-01-19
申请号：EP21194403.8
申请日：2017-03-14
申请人： Cree, Inc.
发明人： VAN BRUNT, Edward Robert , SUVOROV, Alexander V. , PALA, Vipindas , LICHTENWALNER, Daniel J. , ZHANG, Qingchun
IPC分类号： H01L29/872 , H01L21/329 , H01L29/04 , H01L29/06 , H01L29/16 , H01L21/265 , H01L21/04 , H01L29/78 , H01L21/336 , H01L29/10
摘要： Semiconductor devices include a silicon carbide drift region having an upper portion and a lower portion. A first contact is on the upper portion of the drift region and a second contact is on the lower portion of the drift region. The drift region includes a superjunction structure that includes a p-n junction that is formed at an angle of between 10° and 30° from a plane that is normal to a top surface of the drift region. The p-n junction extends within ÷/-1.5° of a crystallographic axis of the silicon carbide material forming the drift region.

3. 发明授权

EP3033771B1 EDGE TERMINATION STRUCTURES FOR HIGH VOLTAGE POWER DEVICES AND METHODS OF MANUFACTURING THE SAME 有权
公开(公告)号：EP3033771B1
公开(公告)日：2019-07-24
申请号：EP14733491.6
申请日：2014-06-10
申请人： Cree, Inc.
发明人： VAN BRUNT, Edward, Robert , PALA, Vipindas , CHENG, Lin , AGARWAL, Anant, Kumar
IPC分类号： H01L29/861 , H01L29/06 , H01L21/329 , H01L29/24

5. 发明公开

EP2973721A1 FIELD EFFECT TRANSISTOR DEVICES WITH BURIED WELL REGIONS AND EPITAXIAL LAYERS 有权
标题翻译： FELDEFFEKTTRANSISTOREN MIT VERBORGENEN VERTIEFUNGSREGIONEN UND EPITAXIALSCHICHTEN
公开(公告)号：EP2973721A1
公开(公告)日：2016-01-20
申请号：EP14779697.3
申请日：2014-03-07
申请人： Cree, Inc.
发明人： PALA, Vipindas , CHENG, Lin , HENNING, Jason , AGARWAL, Anant , PALMOUR, John
IPC分类号： H01L29/66
CPC分类号： H01L29/7802 , H01L21/045 , H01L21/046 , H01L21/049 , H01L29/0878 , H01L29/1095 , H01L29/66068 , H01L29/7828
摘要： A method of forming a transistor device includes providing a drift layer having a first conductivity type and an upper surface, forming first regions in the drift layer and adjacent the upper surface, the first regions having a second conductivity type that is opposite the first conductivity type and being spaced apart from one another, forming a body layer on the drift layer including the source regions, forming spaced apart source regions in the body layer above respective ones of the first regions, forming a vertical conduction region in the body layer between the source regions, the vertical conduction region having the first conductivity type and defining channel regions in the body layer between the vertical conduction region and respective ones of the source regions, forming a gate insulator on the body layer, and forming a gate contact on the gate insulator.
摘要翻译：一种形成晶体管器件的方法包括提供具有第一导电类型和上表面的漂移层，在漂移层中形成第一区域并邻近上表面，第一区域具有与第一导电类型相反的第二导电类型并且彼此间隔开，在包括源极区域的漂移层上形成体层，在主体层中在相应的第一区域上方形成间隔开的源区域，在源层中在源层之间形成垂直传导区域区域，垂直导电区域具有第一导电类型，并且在垂直导电区域和相应源区域之间的体层中限定沟道区域，在主体层上形成栅极绝缘体，并且在栅极绝缘体上形成栅极接触。

6. 发明公开

EP3117463A1 IGBT STRUCTURE FOR WIDE BAND-GAP SEMICONDUCTOR MATERIALS 有权转让
标题翻译： IGBT-STRUKTURFÜRBREITBANDLÜCKEN-HALBLEITERMATERIALIEN
公开(公告)号：EP3117463A1
公开(公告)日：2017-01-18
申请号：EP15745260.8
申请日：2015-01-12
申请人： Cree, Inc.
发明人： PALA, Vipindas , VAN BRUNT, Edward Robert , CHENG, Lin
IPC分类号： H01L29/16 , H01L29/10 , H01L29/739 , H01L29/66
CPC分类号： H01L29/7395 , H01L29/1608 , H01L29/66333
摘要： An IGBT device includes an IGBT stack, a collector contact, a gate contact, and an emitter contact. The IGBT stack includes an injector region, a drift region over the injector region, a spreading region over the drift region, and a pair of junction implants in the spreading region. The spreading region provides a first surface of the IGBT stack, which is opposite the drift region. The pair of junction implants is separated by a channel, and extends from the first surface of the IGBT stack along a lateral edge of the IGBT stack towards the drift region to a first depth, such that the thickness of the spreading region is at least one and a half times greater than the first depth.
摘要翻译： IGBT器件包括IGBT堆叠，集电极触点，栅极触点和发射极触点。 IGBT堆叠包括喷射器区域，喷射器区域上方的漂移区域，漂移区域上的扩展区域以及扩展区域中的一对结植入物。扩展区域提供与漂移区域相对的IGBT堆叠的第一表面。一对结植入物被沟道隔开，并且沿着IGBT堆叠的横向边缘朝着漂移区从第一表面延伸到第一深度，使得扩散区的厚度为至少一个比第一深度大半倍。

7. 发明公开

EP3033771A1 EDGE TERMINATION TECHNIQUE FOR HIGH VOLTAGE POWER DEVICES 有权
标题翻译： EDGINGPROFILE工艺要求高电压权力安排
公开(公告)号：EP3033771A1
公开(公告)日：2016-06-22
申请号：EP14733491.6
申请日：2014-06-10
申请人： Cree, Inc.
发明人： VAN BRUNT, Edward, Robert , PALA, Vipindas , CHENG, Lin , AGARWAL, Anant, Kumar
IPC分类号： H01L29/861 , H01L29/06 , H01L21/329 , H01L29/24
CPC分类号： H01L29/36 , H01L21/0475 , H01L21/322 , H01L29/0615 , H01L29/0661 , H01L29/1608 , H01L29/6606 , H01L29/66068 , H01L29/732 , H01L29/7455 , H01L29/749 , H01L29/7811 , H01L29/7823 , H01L29/861 , H01L29/872
摘要： Embodiments of a semiconductor die having a semiconductor device implemented on the semiconductor die and an edge termination structure around a periphery of the semiconductor device and methods of fabricating the same are disclosed. In one embodiment, a semiconductor die includes a semiconductor device and an edge termination structure around a periphery of the semiconductor device, where the edge termination structure includes negative features (e.g., trenches and/or divots) that vary dose in a corresponding edge termination region to approximate a desired dose profile. In one embodiment, the desired dose profile is a substantially decreasing or substantially linearly decreasing dose from an edge of a main junction of the semiconductor device to an edge of the edge termination region. In this manner, electric field crowding at the edge of the main junction of the semiconductor device is substantially reduced, which in turn substantially improves a break-down voltage of the semiconductor device.

8. 发明公开

EP3031083A1 VERTICAL POWER TRANSISTOR DEVICE 有权
标题翻译：垂直功率晶体管器件
公开(公告)号：EP3031083A1
公开(公告)日：2016-06-15
申请号：EP14752742.8
申请日：2014-08-06
申请人： Cree, Inc.
发明人： PALA, Vipindas , AGARWAL, Anant Kumar , CHENG, Lin , LICHTENWALNER, Daniel Jenner , PALMOUR, John Williams
IPC分类号： H01L29/78 , H01L29/08 , H01L29/10
CPC分类号： H01L29/7802 , H01L29/0684 , H01L29/0865 , H01L29/0878 , H01L29/0882 , H01L29/1095 , H01L29/1608 , H01L29/7827
摘要： A power metal-oxide-semiconductor field-effect transistor (MOSFET) includes a substrate, a drift layer over the substrate, and a spreading layer over the drift layer. The spreading layer includes a pair of junction implants separated by a junction gate field effect (JFET) region. A gate oxide layer is on top of the spreading layer. The gate contact is on top of the gate oxide layer. Each one of the source contacts are on a portion of the spreading layer separate from the gate oxide layer and the gate contact. The drain contact is on the surface of the substrate opposite the drift layer.

9. 发明公开

EP3025372A1 CONTROLLED ION IMPLANTATION INTO SILICON CARBIDE 有权
标题翻译：硅胶中的GESTEUERTE离子注入
公开(公告)号：EP3025372A1
公开(公告)日：2016-06-01
申请号：EP14829761.7
申请日：2014-07-25
申请人： Cree, Inc.
发明人： SUVOROV, Alexander V. , PALA, Vipindas
IPC分类号： H01L29/00 , H01L29/66 , H01L29/872 , H01L21/467 , H01L21/225
CPC分类号： H01L29/1608 , H01L21/046 , H01L21/047 , H01L21/26506 , H01L21/26586 , H01L21/324 , H01L29/0619 , H01L29/0688 , H01L29/0878 , H01L29/1095 , H01L29/6606 , H01L29/66068 , H01L29/66712 , H01L29/7802 , H01L29/7828 , H01L29/861 , H01L29/872
摘要： Methods of forming a semiconductor structure include the use of channeled implants into silicon carbide crystals. Some methods include providing a silicon carbide layer having a crystallographic axis, heating the silicon carbide layer to a temperature of about 300° C. or more, implanting dopant ions into the heated silicon carbide layer at an implant angle between a direction of implantation and the crystallographic axis of less than about 2°, and annealing the silicon carbide layer at a time-temperature product of less than about 30,000° C.-hours to activate the implanted ions.
摘要翻译：根据一些实施例的半导体器件结构包括具有第一导电类型的碳化硅衬底，在碳化硅衬底上具有第一导电类型的碳化硅漂移层，并且具有与碳化硅衬底相对的上表面，以及掩埋结结构在碳化硅漂移层中。掩埋结结构具有与第一导电类型相反的第二导电类型，并且具有大于约一微米的结深度。

10. 发明公开

EP2973723A1 FIELD EFFECT TRANSISTOR DEVICES WITH PROTECTIVE REGIONS 有权转让
标题翻译：与保护区场效应晶体管
公开(公告)号：EP2973723A1
公开(公告)日：2016-01-20
申请号：EP14778304.7
申请日：2014-03-07
申请人： Cree, Inc.
发明人： CHENG, Lin , AGARWAL, Anant , PALA, Vipindas , PALMOUR, John
IPC分类号： H01L29/78
CPC分类号： H01L29/7827 , H01L29/1037 , H01L29/1095 , H01L29/1608 , H01L29/66068 , H01L29/66666 , H01L29/66734 , H01L29/7397 , H01L29/7813
摘要： A transistor device includes a first conductivity type drift layer, a second conductivity type first region in the drift layer, a body layer having the second conductivity type on the drift layer including the first region, a source layer on the body layer, and a body contact region that extends through the source layer and the body layer and into the first region. The transistor device further includes a trench through the source layer and the body layer and extending into the drift layer adjacent the first region. The trench has an inner sidewall facing away from the first region. A gate insulator is on the inner sidewall of the trench, and a gate contact is on the gate insulator.

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