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1. 发明公开

EP0923032A1 Method for transferring data in a multiprocessor computer system with crossbar interconnecting unit 失效
标题翻译：方法um um um em em em em agen agen agen agen agen agen agen agen agen agen agen agen agen agen agen agen agen agen agen
公开(公告)号：EP0923032A1
公开(公告)日：1999-06-16
申请号：EP97830656.1
申请日：1997-12-11
申请人： BULL HN INFORMATION SYSTEMS ITALIA S.p.A.
发明人： Zulian, Ferruccio , Grassi, Antonio
IPC分类号： G06F13/00
CPC分类号： G06F13/1663 , G06F12/0813 , G06F13/1657 , G06F13/4022
摘要： Method (T1-T27) for transferring data in a computer system comprising a plurality of processors and a shared memory, at least one of the processors having a cache memory for storing corresponding data of the shared memory, a plurality of data channels to each of which at least one of the said processors is connected, and means for selectively interconnecting the data channels, the method comprising the steps of requesting (T1-T5) the reading of a data element from the shared memory by a requesting processor, and in the case (T5-T12) in which the requested data element is present in modified form in the cache memory of an intervening processor, transferring (T14-T26) the modified data element from the intervening processor to the interconnecting means and subsequently (T20-T27) to the requesting processor, in which the interconnecting means are granted (T14) access to the data channel corresponding to the requesting processor before the modified data element is available (T19) in the interconnecting means.
摘要翻译：用于在包括多个处理器和共享存储器的计算机系统中传送数据的方法（T1-T27），所述处理器中的至少一个具有用于存储共享存储器的相应数据的高速缓存存储器，所述处理器中的至少一个被连接，以及用于选择性地互连数据信道的装置，所述方法包括以下步骤：由请求处理器请求（T1-T5）从共享存储器读取数据元素;以及在（T5-T12），其中所请求的数据元素以修改的形式存在于中间处理器的高速缓冲存储器中，将修改的数据元素从中间处理器传送（T14-T26）到互连装置，随后（T20-T27））到所述请求处理器，其中所述互连装置被授权（T14）对所述修改的数据元素可用之前对应于所述请求处理器的数据信道（T19）进行访问（T19）连接方式。

2. 发明公开

EP0927935A1 Memory structure with groups of memory banks and serializing means 失效
标题翻译： Speicherstruktur mit Speicherbankgruppen und Serialisierungsvorrichtung
公开(公告)号：EP0927935A1
公开(公告)日：1999-07-07
申请号：EP97830725.4
申请日：1997-12-29
申请人： BULL HN INFORMATION SYSTEMS ITALIA S.p.A.
发明人： Grassi, Antonio , Grassi, Maurizio , Zanzottera, Daniele
IPC分类号： G06F12/06
CPC分类号： G06F12/0607
摘要： Central memory structure for a computer system, comprising a plurality of memory banks (M1a-M3b), each capable of storing data words, control means (Cm) for causing the reading from the memory banks (M1a-M3b) of a data block (W1a-W3b) consisting of a plurality of words requested in a chosen order, in which the memory banks (M1a-M3b) are divided into a plurality of groups (M1a-M3a, M1b-M3b), each comprising at least one memory bank connected to a corresponding data channel (125a, 125b), the words of the data block (W1a-W3b) being distributed among corresponding memory banks of each group (M1a-M3a, M1b-M3b) and the control means (Cm) causing the parallel reading of a word of the data block (W1a-W3b) from each group of memory banks (M1a-M3a, M1b-M3b), in which the memory structure further comprises serializing means (130) for receiving at its input the words read in parallel and for supplying at its output the words read in parallel in a sequence corresponding to the chosen order.
摘要翻译：一种用于计算机系统的中央存储器结构，包括多个可存储数据字的存储体（M1a-M3b），用于使来自数据块的存储体（M1a-M3b）的读取的控制装置（Cm）（ W1a-W3b），其中存储体（M1a-M3b）被分成多个组（M1a-M3a，M1b-M3b），每个组包括至少一个存储体连接到对应的数据通道（125a，125b），数据块（W1a-W3b）的字被分配在各组的相应存储体（M1a-M3a，M1b-M3b）和控制装置（Cm）从存储器组（M1a-M3a，M1b-M3b）组中的数据块（W1a-W3b）的字的并行读取，其中存储器结构还包括串行化装置（130），用于在其输入端接收字并行地并且在其输出处提供以对应于所选择的顺序的顺序并行读取的单词。

3. 发明授权

EP0629952B1 Variable interleaving level memory and related configuration unit 有权转让
标题翻译：存储器variabelerVerschachtelungshöhe和相关配置单元
公开(公告)号：EP0629952B1
公开(公告)日：1999-09-01
申请号：EP93830263.5
申请日：1993-06-16
申请人： Bull HN Information Systems Italia S.p.A.
发明人： Grassi, Antonio , Zanzottera, Daniele
IPC分类号： G06F12/06
CPC分类号： G06F12/0607

4. 发明公开

EP0926599A1 Memory control unit with programmable timing 失效
标题翻译： Speichersteinungeninititheit mit programmierbaren Zeitsignalen
公开(公告)号：EP0926599A1
公开(公告)日：1999-06-30
申请号：EP97830718.9
申请日：1997-12-24
申请人： BULL HN INFORMATION SYSTEMS ITALIA S.p.A.
发明人： Grassi, Antonio , Grassi, Maurizio , Zanzottera, Daniele
IPC分类号： G06F12/00 , G06F13/16
CPC分类号： G06F13/1689 , G06F13/1694 , G11C29/32
摘要： Control unit (Cm) for a central memory (115) of a computer system capable of generating sequences of commands for the said memory (115), each sequence comprising a plurality of commands separated from each other according to a timing defined by periods of a clock signal, in which the control unit (Cm) includes means (230, 233) for programming the timings of the command sequences in the control unit (Cm) installed in the computer system (100).
摘要翻译：用于能够产生所述存储器（115）的命令序列的计算机系统的中央存储器（115）的控制单元（Cm），每个序列包括根据由所述存储器（115）的周期定义的定时彼此分离的多个命令时钟信号，其中控制单元（Cm）包括用于对安装在计算机系统（100）中的控制单元（Cm）中的命令序列的定时进行编程的装置（230,233）。

5. 发明公开

EP0629952A1 Variable interleaving level memory and related configuration unit 有权转让
标题翻译： Speicher mit variabelerVerschachtelungshöheund verwandte Konfigurationseinheit。
公开(公告)号：EP0629952A1
公开(公告)日：1994-12-21
申请号：EP93830263.5
申请日：1993-06-16
申请人： BULL HN INFORMATION SYSTEMS ITALIA S.p.A.
发明人： Grassi, Antonio , Zanzottera, Daniele
IPC分类号： G06F12/06
CPC分类号： G06F12/0607
摘要： A variable interleaving level memory wherein a plurality of independently addressable storage modules are present in a number between 1 and a maximum, comprising a circuit means (14) which, according to the number of the modules present and their capacity, responds to a first field of least-weight address bits (ALOW) and a second field of greater-weight address bits (AHIGH) input thereto by generating a module selection signal for selecting from the various modules present and a plurality of signals (MBIT) representing module address bits, thereby configuring the memory with the highest levels of interleaving and for maximum storage capacity, as allowed for by the number and capacity of the modules present and properly addressing each time the selected module.
摘要翻译：一种可变交错级存储器，其中多个可独立寻址的存储模块以1和最大值之间的数量存在，包括电路装置（14），其根据存在的模块的数量及其容量对第一场通过生成用于从存在的各种模块中选择的模块选择信号和表示模块地址位的多个信号（MBIT）的最小权重地址位（ALOW）和其中输入的较大权重地址位（AHIGH）的第二字段，从而配置具有最高级别的交织和最大存储容量的存储器，如存在的模块的数量和容量所允许的，并且在每次所选择的模块时适当地寻址。

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