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1. 发明授权

EP0296747B1 Integrated circuit with tub tie 失效转让
标题翻译：半导体电路浴缸领带
公开(公告)号：EP0296747B1
公开(公告)日：1997-12-17
申请号：EP88305407.4
申请日：1988-06-14
申请人： AT&T Corp.
发明人： Chen, Min-Liang , Leung, Chung Wai , Wroge, Daniel Mark
IPC分类号： H01L21/82 , H01L21/768
CPC分类号： H01L21/823814 , H01L23/485 , H01L27/0928 , H01L2924/0002 , H01L2924/00

2. 发明公开

EP0366343A3 Integrated circuit fabrication, including low temperature method for making silicide structures 失效转让
标题翻译：集成电路制造，包括制造硅胶结构的低温方法
公开(公告)号：EP0366343A3
公开(公告)日：1990-08-29
申请号：EP89310697.1
申请日：1989-10-18
申请人： AT&T Corp.
发明人： Chen, Min-Liang , Leung, Chung Wai , Martin, Edward P., Jr.
IPC分类号： H01L21/336 , H01L21/3105 , H01L21/316
CPC分类号： H01L21/02129 , H01L21/02271 , H01L21/31625 , H01L21/76801
摘要： In a method of semiconductor integrated circuit fabrication, use of boron and phosphorus doped TEOS (i.e., BPTEOS) as a first-level dielectric permits the dielectric to be flowed at a maximum temperature of 800 o C. Consequently, TiSi₂ source and drain contacts may be used in a field effect transistor without suffering nucleation and consequent increase in grain size, as well as increased resistivity. A layer of TEOS may be deposited before the layer of BPTEOS to prevent sharp corners on the gate from causing thinning and possible breakdown of the BPTEOS layer.

3. 发明授权

EP0366343B1 Integrated circuit fabrication, including low temperature method for making silicide structures 失效转让
标题翻译：集成电路制造，使用低温工艺制造硅化物结构
公开(公告)号：EP0366343B1
公开(公告)日：1996-03-20
申请号：EP89310697.1
申请日：1989-10-18
申请人： AT&T Corp.
发明人： Chen, Min-Liang , Leung, Chung Wai , Martin, Edward P., Jr.
IPC分类号： H01L21/336 , H01L21/3105 , H01L21/316
CPC分类号： H01L21/02129 , H01L21/02271 , H01L21/31625 , H01L21/76801

4. 发明公开

EP0366343A2 Integrated circuit fabrication, including low temperature method for making silicide structures 失效转让
标题翻译：一种集成电路的制造，使用用于产生硅化物结构的低温过程。
公开(公告)号：EP0366343A2
公开(公告)日：1990-05-02
申请号：EP89310697.1
申请日：1989-10-18
申请人： AT&T Corp.
发明人： Chen, Min-Liang , Leung, Chung Wai , Martin, Edward P., Jr.
IPC分类号： H01L21/336 , H01L21/3105 , H01L21/316
CPC分类号： H01L21/02129 , H01L21/02271 , H01L21/31625 , H01L21/76801
摘要： In a method of semiconductor integrated circuit fabrication, use of boron and phosphorus doped TEOS (i.e., BPTEOS) as a first-level dielectric permits the dielectric to be flowed at a maximum temperature of 800 o C. Consequently, TiSi₂ source and drain contacts may be used in a field effect transistor without suffering nucleation and consequent increase in grain size, as well as increased resistivity. A layer of TEOS may be deposited before the layer of BPTEOS to prevent sharp corners on the gate from causing thinning and possible breakdown of the BPTEOS layer.
摘要翻译：在半导体集成电路制造的方法中，使用硼和磷的掺杂TEOS（即，BPTEOS）作为第一级电介质允许电介质在800 C的最大温度下流动因此，的TiSi2源极和漏极触点可以在场效应晶体管中使用而不遭受成核和晶粒尺寸随之增加，以及增加的电阻率。 TEOS的层可以被沉积之前BPTEOS的层，以防止在栅极尖角从曹景伟变薄和BPTEOS层的可能的破坏。

5. 发明公开

EP0521670A1 Method to reduce the number of defects produced by ion implantation and local oxidation processes in semiconductor device manufacturing 失效
标题翻译：一种用于半导体器件的制造过程中减少在离子注入和Lokaloxydierung错误的数目的方法。
公开(公告)号：EP0521670A1
公开(公告)日：1993-01-07
申请号：EP92305934.9
申请日：1992-06-26
申请人： AT&T Corp.
发明人： Gregor, Richard William , Leung, Chung Wai
IPC分类号： H01L21/82 , H01L21/76
CPC分类号： H01L21/32 , H01L21/76221
摘要： Defect density in a semiconductor process sequence that uses two local oxidations is reduced by using an approximately 1:1 ratio of nitride(9) to oxide(4) thickness in the second local oxidation step and an annealing step.
摘要翻译：在做了半导体工艺顺序缺陷密度使用两个本地氧化是通过使用大约1减少：1的比例的氮化物（9）与氧化物（4）厚度的第二局部氧化步骤和退火步骤。

6. 发明公开

EP0482829A1 Method for forming a composite oxide over a heavily doped region 失效
标题翻译：一种用于复合材料的氧化物上的高掺杂的区域中的制备方法。
公开(公告)号：EP0482829A1
公开(公告)日：1992-04-29
申请号：EP91309606.1
申请日：1991-10-17
申请人： AT&T Corp.
发明人： Gregor, Richard William , Leung, Chung Wai , Radosevich, Joseph Rudolph , Roy, Pradip Kumar
IPC分类号： H01L21/76
CPC分类号： H01L21/02238 , H01L21/02255 , H01L21/31662 , H01L21/32 , H01L21/76213
摘要： An oxide region (13) is formed over a heavily doped region ( 15) formed by ion implantation by depositing an oxide layer (11) on a substrate having an oxide-containing surface (3) and heating in an oxidizing atmosphere having a species which moves through the deposited oxide to react with the substrate and form an oxide region (13) between the substrate and deposited oxide layer. The number of defects in the ion implanted, i.e., heavily damaged region, is reduced and the defects do not propagate to regions with good silicon.
摘要翻译：氧化物区域（13）由具有在含氧化物的表面（3）在氧化性气氛中在基板和加热上的氧化层（11）上沉积具有物种形成在通过离子注入形成的重掺杂区域（15），该通过沉积氧化物移动到与基片和沉积氧化物层之间的底物和氧化区域（13）的形式反应。严重受损区域的植入离子的缺陷，即，数目，降低，缺陷不会传播到具有良好的有机硅区域。

7. 发明公开

EP0400877A3 Contact metallization of semiconductor integrated circuit devices 失效
标题翻译：半导体集成电路器件的接触金属化
公开(公告)号：EP0400877A3
公开(公告)日：1991-10-23
申请号：EP90305583.8
申请日：1990-05-23
申请人： AT&T Corp.
发明人： Chen, Min-Liang , Leung, Chung Wai
IPC分类号： H01L23/485 , H01L21/285 , H01L21/90
CPC分类号： H01L21/28518 , H01L21/76838 , H01L23/53223 , H01L2924/0002 , H01L2924/00
摘要： In the manufacture of semiconductor integrated-circuit devices, electrical contact to semiconductor regions (3) such as, e.g., source and drain regions of field-effect transistors typically is made by a structure in which a silicide (91) is intermediary to silicon and metal (11). The invention provides for processing, after window formation and before metal deposition, which includes deposition of a silicide-forming material (92), and annealing in a non-oxidizing atmosphere. Preferably, the atmosphere includes a component which forms a conductive compound (93) with the silicide-forming material. Resulting contact structures have good step coverage, low contact resistance, low interdiffusion of metal into semiconductor, and fail-safe operation in the event of breaks due to electromigration. Moreover, in the case of misalignment of a window, a contact region may be extended laterally by dopant diffusion, thereby safeguarding the junction. Tolerance to window misalignment permits increased packing density, e.g., in dynamic random-access memory arrays.

8. 发明公开

EP0357346A3 CMOS integrated circuit having improved isolation 失效转让
标题翻译：具有改进隔离的CMOS集成电路
公开(公告)号：EP0357346A3
公开(公告)日：1991-09-25
申请号：EP89308621.5
申请日：1989-08-24
申请人： AT&T Corp.
发明人： Chen, Min-Liang , Cochran, William T. , Leung, Chung Wai
IPC分类号： H01L21/76 , H01L21/82
CPC分类号： H01L21/823878 , H01L21/76218 , H01L27/0928
摘要： A p-type tub in a CMOS integrated circuit is isolated from the adjacent n-type tub by means of a field oxide (65) having a p-type channel stop region (66) formed by a boron ion implant. The depth of the ion implant is selected so that the peak of the boron concentration is located immediately under the field oxide region that is subsequently grown. In addition, the implant is allowed to penetrate into the active device regions, producing a retrograde boron concentration in the n-channel region. This technique simultaneously improves device isolation and n-channel transistor punch-through characteristics, allowing the extension of CMOS technology to sub-micron device geometries.

9. 发明公开

EP0400877A2 Contact metallization of semiconductor integrated circuit devices 失效
标题翻译：电子邮件地址：Halbleiterschaltungsvorrichtungen。
公开(公告)号：EP0400877A2
公开(公告)日：1990-12-05
申请号：EP90305583.8
申请日：1990-05-23
申请人： AT&T Corp.
发明人： Chen, Min-Liang , Leung, Chung Wai
IPC分类号： H01L23/485 , H01L21/285 , H01L21/90
CPC分类号： H01L21/28518 , H01L21/76838 , H01L23/53223 , H01L2924/0002 , H01L2924/00
摘要： In the manufacture of semiconductor integrated-circuit devices, electrical contact to semiconductor regions (3) such as, e.g., source and drain regions of field-effect transistors typically is made by a structure in which a silicide (91) is intermediary to silicon and metal (11). The invention provides for processing, after window formation and before metal deposition, which includes deposition of a silicide-forming material (92), and annealing in a non-oxidizing atmosphere. Preferably, the atmosphere includes a component which forms a conductive compound (93) with the silicide-forming material. Resulting contact structures have good step coverage, low contact resistance, low interdiffusion of metal into semiconductor, and fail-safe operation in the event of breaks due to electromigration. Moreover, in the case of misalignment of a window, a contact region may be extended laterally by dopant diffusion, thereby safeguarding the junction. Tolerance to window misalignment permits increased packing density, e.g., in dynamic random-access memory arrays.
摘要翻译：在半导体集成电路器件的制造中，与半导体区域（3）（例如场效应晶体管的源极和漏极区域）的电接触通常由其中硅化物（91）介于硅和金属（11）。本发明提供了窗口形成之后和金属沉积之前的处理，其包括沉积硅化物形成材料（92）并在非氧化气氛中进行退火。优选地，气氛包括与硅化物形成材料形成导电化合物（93）的组分。导致的接触结构具有良好的台阶覆盖率，低接触电阻，金属向半导体的低相互扩散，以及由于电迁移而导致中断的故障安全操作。此外，在窗口未对准的情况下，可以通过掺杂剂扩散横向延伸接触区域，从而保护接合部。对窗口偏移的容限允许增加打包密度，例如在动态随机存取存储器阵列中。

10. 发明授权

EP0357346B1 CMOS integrated circuit having improved isolation 失效转让
标题翻译： CMOS与改性绝缘集成电路
公开(公告)号：EP0357346B1
公开(公告)日：1997-10-22
申请号：EP89308621.5
申请日：1989-08-24
申请人： AT&T Corp.
发明人： Chen, Min-Liang , Cochran, William T. , Leung, Chung Wai
IPC分类号： H01L21/76 , H01L21/82
CPC分类号： H01L21/823878 , H01L21/76218 , H01L27/0928

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