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1. 发明公开

EP1743369A4 MICROPEDE STACKED DIE COMPONENT ASSEMBLY 审中-公开
标题翻译： GESTAPELTE MICROPEDE-CHIPKOMPONENTENBAUGRUPPE
公开(公告)号：EP1743369A4
公开(公告)日：2008-07-09
申请号：EP05735136
申请日：2005-04-12
申请人： VERTICAL CIRCUITS INC
发明人： ROBINSON MARC , VINDASIUS AL , ALMEN DON , JACOBSEN LARRY
IPC分类号： H01L23/02 , H01L23/495 , H01L25/065
CPC分类号： H01L23/49575 , H01L25/0657 , H01L2224/24145 , H01L2225/0652 , H01L2225/06524 , H01L2225/06527 , H01L2225/06551 , H01L2225/06555 , H01L2225/06575 , H01L2225/06579 , H01L2924/09701 , H01L2924/3011
摘要： The present invention provides an apparatus for vertically interconnecting semiconductor die, integrated circuit die, or multiple die segments. Metal rerouting interconnects which extend to one or more sides of the die or segment can be optionally added to the die or multi die segment to provide edge bonding pads upon the surface of the die for external electrical connection points. After the metal rerouting interconnect has been added to the die on the wafer, the wafer is optionally thinned and each die or multiple die segment is singulated from the wafer by cutting or other appropriate singulation method. After the die or multiple die segments are singulated or cut from the wafer, insulation is applied to all surfaces of the die or multiple die segments, openings are made in the insulation above the desired electrical connection pads, and the die or multiple die segments are placed on top of one another to form a stack.. Vertically adjacent segments in the stack are electrically interconnected by attaching a short flexible bond wire or bond ribbon to the exposed electrical connection pad at the peripheral edges of the die which protrudes horizontally from the die and applying electrically conductive polymer, or epoxy, filaments or lines to one or more sides of the stack.
摘要翻译：本发明提供了一种用于垂直互连半导体管芯，集成电路管芯或多个管芯段的装置。延伸到管芯或部分的一个或多个侧面的金属重新布线互连可以可选地被添加到管芯或多管芯部分，以在管芯的表面上为外部电连接点提供边缘接合焊盘。在将金属重布线互连添加到晶片上的管芯上之后，可选地将晶片减薄并且通过切割或其他合适的分割方法将每个管芯或多个管芯分段从晶片切割下来。在将晶粒或多个晶粒片段从晶片上分离或切割之后，对晶粒或多个晶粒片段的所有表面施加绝缘，在所需电连接垫片上方的绝缘体中形成开口，并且将晶粒或多个晶粒片段放置在彼此的顶部以形成堆叠。通过将短的柔性键合线或键合带附接到裸片的外围边缘处的暴露的电连接垫，将堆叠中的垂直相邻的分段电互连，所述裸露的电连接垫从裸片水平突出以及将导电聚合物或环氧树脂，细丝或线施加到叠层的一个或多个侧面。

2. 发明公开

EP1743370A4 THREE DIMENSIONAL SIX SURFACE CONFORMAL DIE COATING 审中-公开
标题翻译： DREIDIMENSIONALE KONFORME SECHSOBERFLÄCHEN-CHIPBESCHICHTUNG
公开(公告)号：EP1743370A4
公开(公告)日：2007-12-05
申请号：EP05736129
申请日：2005-04-12
申请人： VERTICAL CIRCUITS INC
发明人： ROBINSON MARC , VINDASIUS AL
IPC分类号： H01L23/29 , H01L23/053 , H01L23/31
CPC分类号： H01L23/3185 , H01L23/3171 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor die are typically manufactured as a large group of integrated circuit die imaged through photolithographic means on a semiconductor wafer or slice made of silicon. After manufacture, the silicon wafer is thinned, usually by mechanical means, and the wafer is cut, usually with a diamond saw, to singulate the individual die (10). The resulting individual integrated circuit has six exposed surfaces. The top surface of the die includes the circuitry images and any passivation layers that have been added to the to layer during wafer fabrication. The present invention describes a method for protecting and insulating (20) all six surfaces of the die (10) to reduce breakage, provide electrical insulation for these layers, and to provide physical surfaces that can be used for bonding one semiconductor die to another for the purpose of stacking die (10) in an interconnected module or component.
摘要翻译：通常将半导体裸片制造为通过光刻装置在由硅制成的半导体晶片或切片上成像的大量集成电路裸片。在制造之后，通常通过机械手段使硅晶片变薄，并且通常用金刚石锯切割晶片以切割单个管芯（10）。由此产生的单个集成电路具有六个暴露表面。裸片的顶部表面包括电路图像和在晶片制造期间已添加到层的任何钝化层。本发明描述了一种用于保护和绝缘（20）管芯（10）的全部六个表面以减少破损，为这些层提供电绝缘以及提供可用于将一个半导体管芯接合到另一半导体管芯的物理表面的方法将模具（10）堆叠在互连模块或组件中的目的。

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