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1. 发明公开

EP0200372A3 Self-aligned contact window formation in an integrated circuit 失效
标题翻译：在一体化电路中自对准的触点窗口形成
公开(公告)号：EP0200372A3
公开(公告)日：1988-04-27
申请号：EP86302402
申请日：1986-04-01
申请人： INMOS CORPORATION
发明人： Heath, Barbara A.
IPC分类号： H01L21/60 , H01L21/31
CPC分类号： H01L21/76897 , H01L21/033 , H01L21/283 , H01L21/31116
摘要： A process for self-aligned contact window formation in an integrated circuit leaves a "stick" of etch stop on vertical sidewall surfaces to be protected. The process comprises establishing a layer of oxide (24) over active areas and on top of the gate electrode (14, 16) of a transistor. The oxide (24) is thicker on top of the gate electrode than over the active area. A silicon nitride layer (10) acting as an etch stop is included between the oxide and interlevel dielectric (34) such as BPSG. Contact windows (30,32) may deviate from their intended position and partially overlie a poly edge such as a gate electrode or an isolation (field-shield) or field oxide edge. Two- step etching comprises first etching the BPSG down to the etch stop layer, then etching the etch stop and underlying oxide, leaving a "stick" of etch stop on the side of the layer to be protected. This process preserves for the second step of the etch the differential thickness ratio of the oxide over the gate electrodes as compared to the oxide over the active area. This process allows the simultaneous formation of self-aligned contacts the field oxide, field-shield, and gate electrode edges. It is independent of the type of gate dielectric, gate electrode material, and gate electrode sidewall processing.

2. 发明授权

EP0081998B1 Method of fabricating a MOS device on a substrate 失效
标题翻译：在基板上制造MOS器件的方法
公开(公告)号：EP0081998B1
公开(公告)日：1987-03-25
申请号：EP82306613.9
申请日：1982-12-10
申请人： INMOS CORPORATION
发明人： Derbenwick, Gary F. , Adams, James R. , Hanson, Matthew V. , Ryden, William D.
IPC分类号： H01L21/28 , H01L21/82
CPC分类号： H01L27/10844 , H01L21/28273 , H01L29/66833 , H01L29/66954 , Y10S438/981

3. 发明公开

EP0167249A3 Method of making a polysilicon resistor with low thermal activation energy, and such a semiconductor element 有权转让
标题翻译：制造具有低热激活能的多晶硅电阻的方法，以及这样的半导体元件
公开(公告)号：EP0167249A3
公开(公告)日：1986-03-12
申请号：EP85303396
申请日：1985-05-14
申请人： INMOS CORPORATION
发明人： Bourassa, Ronald R. , Butler, Douglas B.
IPC分类号： H01L21/31
CPC分类号： H01L21/324 , H01L21/2686 , H01L21/321 , H01L21/32155 , H01L27/1112 , H01L28/20 , Y10S257/904
摘要： A method of fabricating a resistor in polysilicon and a semiconductor element suitable for use as a load resistor in a static memory. In the method, after the polysilicon has been doped, the device is annealed by exposing it to a rapid increase of ambient temperature (up to between 900 and 1200°C), maintaining the high ambient temperature for a controlled time (about 5 seconds) and then lowering the ambient temperature at a rapid rate. This decreases resistance by one order of magnitude and significantly decreases the temperature activation energy of the resistor. This permits static memory cells to retain data even through the cell has high leakage currents, thereby improving final test yields.

4. 发明授权

EP0049630B1 Dummy cell arrangement for an MOS memory 失效
标题翻译： MOS存储器的虚拟单元排列
公开(公告)号：EP0049630B1
公开(公告)日：1986-02-12
申请号：EP81304604.2
申请日：1981-10-05
申请人： INMOS CORPORATION
发明人： Heightley, John D. , Eaton, Sargent Sheffield, Jr.
IPC分类号： G11C11/24
CPC分类号： G11C11/4099

5. 发明公开

EP0129661A3 Bootstrap driver circuits for a MOS memory 失效
标题翻译：用于MOS存储器的BOOTSTRAP驱动电路
公开(公告)号：EP0129661A3
公开(公告)日：1985-07-10
申请号：EP84104304
申请日：1981-06-25
申请人： INMOS CORPORATION
发明人： Sud, Rahul , Hardee, Kim Carver
IPC分类号： H03K05/02 , H03K19/003 , H03K19/094 , G11C08/00
CPC分类号： H03K19/01735 , G11C7/12 , G11C8/08 , H03K5/023 , H03K19/01855
摘要： A high speed, low power bootstrap driver is disclosed for use in an MOS memory. The basic driver includes first and second enhancement mode transistors (12a, 14a) for receiving a digital input (16a). The drain of the first transistor (12a) is coupled to a high impedance depletion mode transistor (22a), and the drain ofthe latter transistor is coupled to the source of a low impedance transistor (26a). Another enhancement mode transistor (30a) is coupled via its sources to the drain of the second enhancement mode transistor (14a) and is coupled via its gate to the drain of the first enhancement mode transistor (12a). A capacitor (34a) is connected between the drain of the high impedance transistor (22a) and the drain of the second enhancement mode transistor (14a). When a low level input is received, the drain of the first enhancement mode transistor (12a) is rapidly bootstrapped to a high level voltage above the positive power supply for use as an output signal (18a). Delay means, such as an inverter (46, 48), are arranged to receive the input signal and apply a delayed input signal to the gates of said first and second enhancement mode transistors (12a, 14a).

6. 发明公开

EP0129661A2 Bootstrap driver circuits for a MOS memory 失效
标题翻译： “Bootstrap” - 电视剧“莫斯科演唱会”。
公开(公告)号：EP0129661A2
公开(公告)日：1985-01-02
申请号：EP84104304.5
申请日：1981-06-25
申请人： INMOS CORPORATION
发明人： Sud, Rahul , Hardee, Kim Carver
IPC分类号： H03K5/02 , H03K19/003 , H03K19/094 , G11C8/00
CPC分类号： H03K19/01735 , G11C7/12 , G11C8/08 , H03K5/023 , H03K19/01855
摘要： A high speed, low power bootstrap driver is disclosed for use in an MOS memory. The basic driver includes first and second enhancement mode transistors (12a, 14a) for receiving a digital input (16a). The drain of the first transistor (12a) is coupled to a high impedance depletion mode transistor (22a), and the drain ofthe latter transistor is coupled to the source of a low impedance transistor (26a). Another enhancement mode transistor (30a) is coupled via its sources to the drain of the second enhancement mode transistor (14a) and is coupled via its gate to the drain of the first enhancement mode transistor (12a). A capacitor (34a) is connected between the drain of the high impedance transistor (22a) and the drain of the second enhancement mode transistor (14a). When a low level input is received, the drain of the first enhancement mode transistor (12a) is rapidly bootstrapped to a high level voltage above the positive power supply for use as an output signal (18a). Delay means, such as an inverter (46, 48), are arranged to receive the input signal and apply a delayed input signal to the gates of said first and second enhancement mode transistors (12a, 14a).
摘要翻译：公开了用于MOS存储器的高速，低功率自举驱动器。基本驱动器包括用于接收数字输入（16a）的第一和第二增强型晶体管（12a，14a）。第一晶体管（12a）的漏极耦合到高阻耗耗模式晶体管（22a），并且后一晶体管的漏极耦合到低阻抗晶体管（26a）的源极。另一增强型晶体管（30a）经由其源耦合到第二增强型晶体管（14a）的漏极，并经由其栅极耦合到第一增强型晶体管（12a）的漏极。在高阻抗晶体管（22a）的漏极和第二增强型晶体管（14a）的漏极之间连接有电容器（34a）。当接收到低电平输入时，第一增强型晶体管（12a）的漏极被快速自举到正电源上方的高电平电压，用作输出信号（18a）。诸如反相器（46,48）的延迟装置被布置成接收输入信号并将延迟的输入信号施加到所述第一和第二增强型晶体管（12a，14a）的栅极。

7. 发明公开

EP0044628A3 Redundancy scheme for an MOS memory 失效
标题翻译：一个MOS记忆的冗余计划
公开(公告)号：EP0044628A3
公开(公告)日：1983-08-10
申请号：EP81302870
申请日：1981-06-25
申请人： INMOS CORPORATION
发明人： Hardee, Kim Carver , Sud, Rahul , Heightley, John D.
IPC分类号： G06F11/20
CPC分类号： G11C29/785 , G11C29/808
摘要： An MOS memory has a main array of memory cells (10, 12) and a plurality of spare memory cells (22, 24). Typically, each memory cell is tested for operability by a conventional probe test. A redundancy scheme is provided for substituting spare memory cells for memory cells found to be defective. An on-chip address controller (38-50) responds to the probe test finding a defective cell by permanently storing and rendering continuously available a fully asynchronous electrical indication of the address of the defective cell. The address controller (38-50) compares its stored data with memory cell information received during normal memory operation, and generates a control signal indicative of the receipt of an address which corresponds to a defective cell. A spare cell selector (106, 108) responds to the control signal by electrically accessing a spare memory cell and by prohibiting access of the defective memory cell.

8. 发明公开

EP0081998A2 Method of fabricating a MOS device on a substrate 失效
标题翻译： Verfahren zur Herstellung einer MOS Anordnung auf einem Substrat。
公开(公告)号：EP0081998A2
公开(公告)日：1983-06-22
申请号：EP82306613.9
申请日：1982-12-10
申请人： INMOS CORPORATION
发明人： Derbenwick, Gary F. , Adams, James R. , Hanson, Matthew V. , Ryden, William D.
IPC分类号： H01L21/28 , H01L21/82
CPC分类号： H01L27/10844 , H01L21/28273 , H01L29/66833 , H01L29/66954 , Y10S438/981
摘要： The method of the invention is for fabricating MOS devices of the type found in very large scale integrated circuits. Electrodes (36,44) and isolating layers (38,46) are fabricated independently of each other in order to independently tailor their thicknesses and thereby provide improved isolation between the gate electrodes (36, 44) and interconnects (42) and independently controllable operating characteristics for multiple gate electrode structures. The method is employed for the fabrication of a dynamic RAM memory cell, an overlapping gate CCD device and a selfaligned MNOS transistor cell.
摘要翻译：本发明的方法是用于制造在大规模集成电路中发现的类型的MOS器件。彼此独立地制造电极（36,44）和隔离层（38,46），以便独立地定制其厚度，从而提供栅电极（36,44）和互连（42）之间的改进隔离，并且可独立控制操作多栅电极结构的特性。该方法用于制造动态RAM存储器单元，重叠栅极CCD器件和自对准MNOS晶体管单元。

9. 发明公开

EP0081951A2 A semiconductor memory cell 失效
标题翻译： Halbleiterspeicherzelle。
公开(公告)号：EP0081951A2
公开(公告)日：1983-06-22
申请号：EP82306417.5
申请日：1982-12-02
申请人： INMOS CORPORATION
发明人： Lancaster, Arthur L.
IPC分类号： H01L29/60 , G11C11/34
CPC分类号： H01L29/792
摘要： A semiconductor memory cell of reduced size for a semiconductor memory having rows of such memory cells. The cell is a non-volatile memory cell and includes first (A) and second (C) gates insulated from a silicon substrate (26) to form a pair of MOS transistors. A storage transistor is formed by a third gate (B) which is disposed between the other two gates (A and C) and which in insulated from the substrate (26) by material (36, 38) suitable for forming a storage transistor with the third gate (B). A drain region (14) is disposed in the substrate preferably adjacent to the second gate (C) and a source region is disposed in the substrate preferably adjacent to the first gate (A). Thus, the first gate (A) can isolate the storage transistor from the source region (16) to permit the source to be coupled to other cells in the same row and thereby act as a common source for an entire row of cells.
摘要翻译：一种具有这种存储单元行的半导体存储器的尺寸减小的半导体存储单元。该单元是非易失性存储单元，并且包括与硅衬底（26）绝缘的第一（A）和第二（C）栅极，以形成一对MOS晶体管。存储晶体管由设置在其它两个栅极（A和C）之间的第三栅极（B）形成，并且通过适于形成存储晶体管的材料（36,38）与衬底（26）绝缘，第三门（B）。漏极区域（14）设置在衬底中，优选地邻近第二栅极（C），并且源区域优选地设置在衬底中，优选地邻近于第一栅极（A）。因此，第一栅极（A）可以将存储晶体管与源极区域（16）隔离，以允许源极耦合到同一行中的其它单元，从而充当整行单元的公共源。

10. 发明公开

EP0066974A2 Improved substrate bias generator 失效
标题翻译：用于集成电路的电源模块。
公开(公告)号：EP0066974A2
公开(公告)日：1982-12-15
申请号：EP82302480.7
申请日：1982-05-14
申请人： INMOS CORPORATION
发明人： Slemmer, William Carl
IPC分类号： G06F1/04 , G05F3/20 , G11C5/00
CPC分类号： G05F3/205
摘要： An improved substrate bias generator for MOS integrated circuits is described. The generator includes circuitry (45, 70) for generating two trains of periodic pulses which are approximately phase opposite, one of the pulse trains being slightly delayed as compared to the other pulse train. The two pulse trains are applied to a pumping circuit (85) which generates a target voltage and initially transfers a positive charge into the substrate, and thereafter transfers a positive charge out of the substrate. The positive charge transferred out of the substrate is greater than the positive charge transferred into the substrate when the absolute value of the potential on the substrate is less than the target voltage. Otherwise, a net positive charge is transferred into the substrate. In this manner, the absolute value of the potential on the substrate is driven towards the target voltage.

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