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81. 发明公开

EP3022655A2 COMPUTING ARCHITECTURE WITH PERIPHERALS 审中-公开
标题翻译：与外围设备计算机体系结构
公开(公告)号：EP3022655A2
公开(公告)日：2016-05-25
申请号：EP14771622.9
申请日：2014-07-17
申请人： Synaptic Laboratories Limited
发明人： GITTINS, Benjamin
IPC分类号： G06F13/16
CPC分类号： G06F13/364 , G06F3/0619 , G06F3/065 , G06F3/067 , G06F12/0811 , G06F12/0815 , G06F12/082 , G06F12/0831 , G06F12/0864 , G06F13/1663 , G06F13/20 , G06F13/372 , G06F13/4068 , G06F13/4282 , G06F2212/283 , G06F2212/6032 , G06F2212/621 , G11C7/1072
摘要： A shared memory computing architecture (300) has M interconnect masters (350, 351, 352, 353, 354), one interconnect target (370), and a timeslot based interconnect (319). The interconnect (319) has a unidirectional timeslot based interconnect (320) to transport memory transfer requests with T timeslots and a unidirectional timeslot based interconnect (340) to transport memory transfer responses with R timeslots. For each of the R timeslots, that timeslot: corresponds to one memory transfer request timeslot and starts at least L clock cycles after the start time of that corresponding memory request timeslot. The value of L is >= 3 and

82. 发明公开

EP2862095A4 INTELLIGENT ADAPTER 审中-公开
标题翻译：智能适配器
公开(公告)号：EP2862095A4
公开(公告)日：2016-03-02
申请号：EP13803862
申请日：2013-05-28
申请人： QLOGIC CORP
发明人： SHAH SHISHIR
IPC分类号： G06F3/06 , G06F12/08 , H04L29/08
CPC分类号： G06F3/0604 , G06F3/0605 , G06F3/061 , G06F3/0634 , G06F3/0649 , G06F3/0653 , G06F3/0655 , G06F3/0656 , G06F3/0665 , G06F3/067 , G06F3/0683 , G06F3/0685 , G06F12/0238 , G06F12/08 , G06F12/0815 , H04L67/1097

83. 发明公开

EP2946298A1 CONTEXT SWITCHING WITH OFFLOAD PROCESSORS 无效
标题翻译：具有输出PROCESSORS上下文切换
公开(公告)号：EP2946298A1
公开(公告)日：2015-11-25
申请号：EP13872212.9
申请日：2013-06-26
申请人： Xockets IP LLC
发明人： DALAL, Parin , BELAIR, Stephen
IPC分类号： G06F13/00
CPC分类号： G06F13/1652 , G06F9/3877 , G06F9/461 , G06F9/4843 , G06F12/0815 , G06F12/0875 , G06F13/16 , G06F13/285 , G06F13/362 , G06F13/4022 , G06F13/4068 , G06F15/161 , G06F15/17337 , H04L29/08135 , H04L29/08549 , H04L47/193 , H04L47/2441 , H04L47/56 , H04L47/624 , H04L47/6295 , H04L49/40 , H04L49/90 , H04L61/103 , H04L61/2592 , H04L61/6086 , Y02D10/14 , Y02D10/151
摘要： A method for context switching of multiple offload processors is disclosed. The method can include receiving network packets for processing through a memory bus connected socket, organizing the network packets into multiple sessions for processing, suspending processing of at least one session by reading a cache state of at least one of the offload processor into a context memory by operation of a scheduling circuit, with virtual memory locations and physical cache locations being aligned, and subsequently directing transfer of the cache state to at least one of the offload processors for processing by operation of the scheduling circuit.

84. 发明公开

EP2764516A4 SELF-JOURNALING AND HIERARCHICAL CONSISTENCY FOR NON-VOLATILE STORAGE 审中-公开
标题翻译： SELBSTHISTORISIERUNG UND HIERARCHISCHE KONSISTENZFÜRNICHTFLÜCHTIGESPEICHER
公开(公告)号：EP2764516A4
公开(公告)日：2015-07-08
申请号：EP12838511
申请日：2012-10-04
申请人： LSI CORP
发明人： COHEN EARL T , CANEPA TIMOTHY L
IPC分类号： G11C16/02 , G06F12/00 , G11C16/06
CPC分类号： G06F12/0246 , G06F11/07 , G06F12/0815 , G06F2212/1032 , G06F2212/621 , G06F2212/7201 , G06F2212/7207 , G11C16/02 , G11C16/06
摘要： A non-volatile storage system having Non-Volatile Memory (NVM) provides self-journaling and hierarchical consistency, enabling low-latency recovery and force unit access handshake. Mappings between host addresses and addresses in the NVM are maintained via one or more map entries, enabling locating of host data written to the NVM. Objects stored in the NVM include sufficient information to recover the object solely within the object itself. The NVM is managed as one or more data streams, a map stream, and a checkpoint stream. Host data is written to the data streams, map entries are written to the map stream, and checkpoints of map entries and other data structures are written to the checkpoint stream. Time markers embedded in the streams enable determination, during recovery, that selected portions of the streams are inconsistent with each other and are to be discarded.
摘要翻译：具有非易失性存储器（NVM）的非易失性存储系统提供自我日记和分级一致性，实现低延迟恢复和强制单元访问握手。通过一个或多个地图条目维护NVM中的主机地址和地址之间的映射，从而可以定位写入NVM的主机数据。存储在NVM中的对象包括足够的信息，仅在对象本身内恢复对象。 NVM被管理为一个或多个数据流，地图流和检查点流。主机数据被写入数据流，地图条目被写入地图流，地图条目和其他数据结构的检查点被写入检查点流。嵌入在流中的时间标记使得能够在恢复期间确定流的所选部分彼此不一致并被丢弃。

85. 发明公开

EP2879058A1 Parallel computer system, control method of parallel computer system, information processing device, arithmetic processing device, and communication control device 有权
标题翻译：用于并行计算机系统，信息处理装置，算术处理设备和通信控制装置并行计算机系统的控制方法
公开(公告)号：EP2879058A1
公开(公告)日：2015-06-03
申请号：EP14192720.2
申请日：2014-11-11
申请人： FUJITSU LIMITED
发明人： Hiramoto, Shinya , Inoue, Tomohiro , Maeda, Masahiro , Ando, Shun , Toyoda, Yuta
IPC分类号： G06F12/08 , G06F9/52
CPC分类号： G06F12/0804 , G06F9/526 , G06F12/0811 , G06F12/0815 , G06F12/0842 , G06F2212/1024 , G06F2212/283
摘要： A parallel computer system includes information processing devices, each of the information processing devices including a communication control device that performs communication, a main memory that stores data, and an arithmetic processing device that is coupled to the communication control device and the main memory, the information processing devices being coupled to each other through a network by the respective communication control device, wherein the arithmetic processing device includes a cache memory and a cache controller, the cache controller that executes an atomic operation for target data on the cache memory that stores the target data when the communication control device outputs an atomic operation request that is used to request the atomic operation, the atomic operation being not divided into a smaller operation, and notifies the communication control device of a result that is obtained by executing the atomic operation on the cache memory.
摘要翻译：并行计算机系统包括信息处理装置，每个包括通信控制设备的信息处理设备的没有进行通信，主存储器没有存储数据，并且运算处理装置也被连接到通信控制装置和所述主存储器，所述信息处理设备通过由respectivement通信控制装置，worin的算术处理装置包括高速缓存存储器和高速缓存控制器的网络彼此耦合，高速缓存控制器那样执行关于原子操作用于在高速缓冲存储器中的目标数据没有存储当通信控制装置输出到原子操作请求并用于请求的原子操作目标数据，原子操作被不分成更小的操作，并通知其结果的通信控制装置并通过执行原子操作所获得高速缓存存储器。

86. 发明公开

EP2869194A1 EXTENDED CACHE COHERENCE PROTOCOL-BASED MULTI-LEVEL COHERENCE DOMAIN SIMULATION VERIFICATION AND TEST METHOD 审中-公开
标题翻译：测试和测试PROCEDURE ON与多级一致性EXTENDED缓存的一致性基于域仿真甲LOG
公开(公告)号：EP2869194A1
公开(公告)日：2015-05-06
申请号：EP13872015.6
申请日：2013-10-11
申请人： Inspur Electronic Information Industry Co., Ltd.
发明人： WANG, Endong , HU, Leijun , CHEN, Jicheng , ZHANG, Feng , ZHOU, Hengzhao , FU, Yunyue , GAN, Xiaowei
IPC分类号： G06F9/455
CPC分类号： G06F11/3608 , G06F11/3664 , G06F12/0815 , G06F12/0837 , G06F17/5009 , G06F2212/2542 , G06F2212/621
摘要： An extension Cache Coherence protocol-based multi-level coherency domain simulation verification and test method. An extension Cache Coherence protocol-based multi-level coherency domain CC-NUMA (Cache Coherent Non-Uniform Memory Access) system protocol simulation model is built, a protocol table inquiring and state converting executing mechanism in a key node of a system ensures that a Cache Coherence protocol is maintained in a single computing domain and is simultaneously maintained among a plurality of computing domains, and accuracy and stability of intra-domain and inter-domain transmission are ensured; a credible protocol inlet conversion coverage rate evaluation driven verification method is provided, transactions are processed by loading an optimized transaction generator push model, a coverage rate index is obtained after the operation is ended, and the verification efficiency is increased in comparison with a random transaction promoting mechanism. Through building a multi-processor multi-level coherency domain verification system model and performing relevant simulation verification, the applicability and the effectiveness of the method are further confirmed.

87. 发明公开

EP2862095A2 INTELLIGENT ADAPTER 审中-公开
标题翻译：智能适配器
公开(公告)号：EP2862095A2
公开(公告)日：2015-04-22
申请号：EP13803862.5
申请日：2013-05-28
申请人： Qlogic Corporation
发明人： SHAH, Shishir
IPC分类号： G06F15/16
CPC分类号： G06F3/0604 , G06F3/0605 , G06F3/061 , G06F3/0634 , G06F3/0649 , G06F3/0653 , G06F3/0655 , G06F3/0656 , G06F3/0665 , G06F3/067 , G06F3/0683 , G06F3/0685 , G06F12/0238 , G06F12/08 , G06F12/0815 , H04L67/1097
摘要： A network device that includes a storage protocol controller having a port for interfacing with a storage area network (SAN) based storage device and another network device operating within a cluster is provided. The network device also includes a processor executing instructions for managing a local storage device that is configured to operate as a caching device for a computing device. The network device is configured to operate as a host bus adapter and a storage controller for managing storage space at the local storage device and the SAN-based storage device.
摘要翻译：提供了一种包括存储协议控制器的网络设备，该存储协议控制器具有用于与基于存储区域网络（SAN）的存储设备和在群集内操作的另一个网络设备接口的端口。网络设备还包括执行用于管理本地存储设备的指令的处理器，该本地存储设备被配置为作为用于计算设备的高速缓存设备来操作。网络设备被配置为作为主机总线适配器和用于管理本地存储设备和基于SAN的存储设备处的存储空间的存储控制器来操作。

88. 发明授权

EP2666092B1 SYSTEME MULTI-COEURS ET PROCEDE DE COHERENCE DE DONNEES 有权
标题翻译：更多核心系统和数据的一致性程序
公开(公告)号：EP2666092B1
公开(公告)日：2015-02-25
申请号：EP11804704.2
申请日：2011-12-23
申请人： Commissariat à l'Énergie Atomique et aux Énergies Alternatives
发明人： CUDENNEC, Loïc , KOFUJI, Jussara , ACQUAVIVA, Jean-Thomas , CAMIER, Jean-Sylvain
IPC分类号： G06F12/08
CPC分类号： G06F12/084 , G06F12/0292 , G06F12/0815 , G06F12/0831

89. 发明公开

EP2430551A4 CACHE COHERENT SUPPORT FOR FLASH IN A MEMORY HIERARCHY 有权
标题翻译： ZWISCHENSPEICHERKOHÄRENTE支持对于Flash存储器层级
公开(公告)号：EP2430551A4
公开(公告)日：2015-01-07
申请号：EP10775527
申请日：2010-05-13
申请人： ORACLE AMERICA INC
发明人： KAPIL SANJIV , HETHERINGTON RICKY C
IPC分类号： G06F12/08 , G06F12/12 , G06F13/16
CPC分类号： G06F12/08 , G06F12/0808 , G06F12/0811 , G06F12/0815 , G06F12/123 , G06F2212/1024 , G06F2212/205 , G06F2212/683 , G06F2212/7203
摘要： System and method for using flash memory in a memory hierarchy. A computer system includes a processor coupled to a memory hierarchy via a memory controller. The memory hierarchy includes a cache memory, a first memory region of random access memory coupled to the memory controller via a first buffer, and an auxiliary memory region of flash memory coupled to the memory controller via a flash controller. The first buffer and the flash controller are coupled to the memory controller via a single interface. The memory controller receives a request to access a particular page in the first memory region. The processor detects a page fault corresponding to the request and in response, invalidates cache lines in the cache memory that correspond to the particular page, flushes the invalid cache lines, and swaps a page from the auxiliary memory region to the first memory region.

90. 发明公开

EP2788880A1 EFFICIENT STORAGE OF META-BITS WITHIN A SYSTEM MEMORY 有权
标题翻译：荟萃BITS在系统存储器存储效率
公开(公告)号：EP2788880A1
公开(公告)日：2014-10-15
申请号：EP12856495.2
申请日：2012-11-16
申请人： International Business Machines Corporation
发明人： DODSON, John Steven , GOODMAN, Benjiman L. , HNATKO, Steven J. , WRIGHT, Kenneth L.
IPC分类号： G06F12/08
CPC分类号： G06F11/1076 , G06F11/1064 , G06F12/0815 , G06F12/0895 , G11C2029/0411
摘要： Mechanisms are provided for efficient storage of meta-bits within a system memory. The mechanisms combine an L/G bit and an SUE bit to form meta-bits. The mechanisms then determine the local/global state of a cache line on the first cycle of data. The mechanisms forward the data to the requesting cache, and the requesting cache may reissue the request globally based on the local/global state of the cache line. The mechanisms then determine the special uncorrectable error state of the cache line on the second or subsequent cycle of data. The mechanisms perform error processing regardless of whether the request was reissued globally.

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