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1. 发明公开

EP2946298A1 CONTEXT SWITCHING WITH OFFLOAD PROCESSORS 无效
标题翻译：具有输出PROCESSORS上下文切换
公开(公告)号：EP2946298A1
公开(公告)日：2015-11-25
申请号：EP13872212.9
申请日：2013-06-26
申请人： Xockets IP LLC
发明人： DALAL, Parin , BELAIR, Stephen
IPC分类号： G06F13/00
CPC分类号： G06F13/1652 , G06F9/3877 , G06F9/461 , G06F9/4843 , G06F12/0815 , G06F12/0875 , G06F13/16 , G06F13/285 , G06F13/362 , G06F13/4022 , G06F13/4068 , G06F15/161 , G06F15/17337 , H04L29/08135 , H04L29/08549 , H04L47/193 , H04L47/2441 , H04L47/56 , H04L47/624 , H04L47/6295 , H04L49/40 , H04L49/90 , H04L61/103 , H04L61/2592 , H04L61/6086 , Y02D10/14 , Y02D10/151
摘要： A method for context switching of multiple offload processors is disclosed. The method can include receiving network packets for processing through a memory bus connected socket, organizing the network packets into multiple sessions for processing, suspending processing of at least one session by reading a cache state of at least one of the offload processor into a context memory by operation of a scheduling circuit, with virtual memory locations and physical cache locations being aligned, and subsequently directing transfer of the cache state to at least one of the offload processors for processing by operation of the scheduling circuit.

2. 发明公开

EP2828741A1 METHOD IN A PROCESSOR, AN APPARATUS AND A COMPUTER PROGRAM PRODUCT 审中-公开
标题翻译：过程中的处理器，设备和计算机程序产品
公开(公告)号：EP2828741A1
公开(公告)日：2015-01-28
申请号：EP12871972.1
申请日：2012-03-21
申请人： Nokia Corporation
发明人： LÄHTEENMÄKI, Mika
IPC分类号： G06F9/38 , G06F9/50 , G06F9/48 , G06F15/16
CPC分类号： G06F9/3869 , G06F9/30174 , G06F9/3836 , G06F9/3867 , G06F9/3885 , G06F15/17337 , G06F15/80
摘要： There is disclosed a method in which a pipelining instruction is received by a first processor core of a multicore processor. Information in the pipelining instruction is used to determine a connection between a first functional unit in the first processor core and a second functional unit in a second processor core of the multicore processor. A switch is controlled to form a pipeline comprising the first functional unit and the second functional unit to enable data communication connection between an output of the first functional unit and an input of the second functional unit. The method may further comprise using a translation unit to translate an instruction of an instruction set of a first processor core to a corresponding instruction or a sequence of instructions of an instruction set of the second processor core. There is also disclosed an apparatus and a computer program product to implement the method.

3. 发明公开

EP2579164A1 MULTIPROCESSOR SYSTEM, EXECUTION CONTROL METHOD, EXECUTION CONTROL PROGRAM 有权
标题翻译：多功能体系，澳大利亚卫生组织，澳大利亚卫生组织
公开(公告)号：EP2579164A1
公开(公告)日：2013-04-10
申请号：EP11786619.4
申请日：2011-05-24
申请人： NEC Corporation
发明人： TAKEUCHI, Toshiki , IGURA, Hiroyuki
IPC分类号： G06F15/167 , G06F13/12 , G06F13/362
CPC分类号： G06F15/17337
摘要： The multiprocessor system includes one or a plurality of main processors and a plurality of sub-processors, and an execution control circuit which conducts execution control of each the sub-processors, wherein the execution control circuit includes an execution control processor for execution control processing of each the sub-processors, a control bus output unit for activation of a command to each the sub-processors, a status bus input unit for status notification from each the sub-processors, a determination circuit which determiners whether or not the status notification has one-to-one dependency with a processing command to be issued next on an operation sequence and is to be processed at a high speed, a status accelerator which issues a corresponding processing activation command when the status notification is to be processed at a high speed, and a status FIFO control unit which processes the status notification by using the execution control processor.
摘要翻译：多处理器系统包括一个或多个主处理器和多个子处理器，以及执行每个子处理器的执行控制的执行控制电路，其中执行控制电路包括用于执行控制处理的执行控制处理器每个子处理器，用于激活每个子处理器的命令的控制总线输出单元，用于来自每个子处理器的状态通知的状态总线输入单元，确定状态通知是否具有的确定电路一个一对一的依赖关系，下一个要在操作序列上发出的处理命令的依赖关系，并且要高速处理的状态加速器，当状态通知要高速处理时发出相应的处理激活命令以及通过使用执行控制处理器来处理状态通知的状态FIFO控制单元。

4. 发明公开

EP1615138A3 Multiprocessor chip having bidirectional ring interconnect 审中-公开
标题翻译：多个计算机芯片与一个双向环互连
公开(公告)号：EP1615138A3
公开(公告)日：2009-03-04
申请号：EP05253224.9
申请日：2005-05-25
申请人： Intel Corporation
发明人： Chrysos, George , Mattina, Matthew , Felix, Stephen
IPC分类号： G06F15/173 , H04L12/42
CPC分类号： G06F15/8015 , G06F15/17337
摘要： Embodiments of the present invention are related in general to on-chip integration of multiple components on a single die and in particular to on-chip integration of multiple processors via a bidirectional ring interconnect. An embodiment of a semiconductor chip includes a plurality of processors, an address space shared between the processors, and a bidirectional ring interconnect to couple the processors and the address space. An embodiment of a method includes calculating distances between a packet source and destination on multiple ring interconnects, determining on which interconnect to transport the packet, and then transporting the packet on the determined interconnect. Embodiments provide improved latency and bandwidth in a multiprocessor chip. Exemplary applications include chip multiprocessing.

5. 发明公开

EP1615138A2 Multiprocessor chip having bidirectional ring interconnect 审中-公开
标题翻译： Mehrrechnerchip mit einer Bidirektionellen Ringverbindung
公开(公告)号：EP1615138A2
公开(公告)日：2006-01-11
申请号：EP05253224.9
申请日：2005-05-25
申请人： INTEL CORPORATION
发明人： Chrysos, George , Mattina, Matthew , Felix, Stephen
IPC分类号： G06F15/173 , H04L12/42
CPC分类号： G06F15/8015 , G06F15/17337
摘要： Embodiments of the present invention are related in general to on-chip integration of multiple components on a single die and in particular to on-chip integration of multiple processors via a bidirectional ring interconnect. An embodiment of a semiconductor chip includes a plurality of processors, an address space shared between the processors, and a bidirectional ring interconnect to couple the processors and the address space. An embodiment of a method includes calculating distances between a packet source and destination on multiple ring interconnects, determining on which interconnect to transport the packet, and then transporting the packet on the determined interconnect. Embodiments provide improved latency and bandwidth in a multiprocessor chip. Exemplary applications include chip multiprocessing.
摘要翻译：本发明的实施例一般涉及单个管芯上的多个部件的片上集成，特别是通过双向环形互连进行多个处理器的片上集成。半导体芯片的实施例包括多个处理器，处理器之间共享的地址空间以及耦合处理器和地址空间的双向环形互连。一种方法的实施例包括计算多个环互连上的分组源和目的地之间的距离，确定传输分组的哪个互连，然后在确定的互连上传输分组。实施例在多处理器芯片中提供改进的等待时间和带宽。示例性应用包括芯片多处理。

6. 发明公开

EP1408417A1 Efficient messaging in a parallel processing system 审中-公开
标题翻译： Eeiziente Benachrichtung in einem parallelen Verarbeitungsystem
公开(公告)号：EP1408417A1
公开(公告)日：2004-04-14
申请号：EP02017329.0
申请日：2002-08-01
申请人： Fujitsu Siemens Computers, LLC
发明人： Myers, Mark S.
IPC分类号： G06F15/173
CPC分类号： G06F15/17337
摘要： The present invention, generally speaking, provides an efficient method of sending a long message from a first compute node to a second compute node across an interconnection network. In the first compute node, a message header field is set to a predetermined value and the message is sent. In the second compute node, the message header is received and processed, and a memory location is read in accordance with the contents of a base address register and an index register. Using Direct Memory Access, the message is then stored in memory at a storage address determined in accordance with the contents of the memory location. Preferably, the storage address is aligned on a memory page boundary.
摘要翻译：该方法涉及第一计算节点将消息头字段设置为预定值并发送消息，并且第二计算节点接收和处理消息头，以及根据基地址寄存器和索引的内容读取存储器位置寄存器。第二计算节点还使用直接存储器访问在存储器中以根据存储器位置的内容确定的存储地址存储该消息。

7. 发明公开

EP1367499A1 Compute node to mesh interface for highly scalable parallel processing system 审中-公开
标题翻译： Rechnerknoten zur Maschenschnittstellefürhoch skalierbares paralleles Verarbeitungsystem
公开(公告)号：EP1367499A1
公开(公告)日：2003-12-03
申请号：EP02011858.4
申请日：2002-05-28
申请人： Fujitsu Siemens Computers, LLC
发明人： Myers, Mark S.
IPC分类号： G06F15/173
CPC分类号： G06F15/17337
摘要： An interface circuit for interfacing one or more compute nodes to a mesh is capable of serving a wide range of MPP systems. The interface circuit includes a first bus interface for interfacing with a first bus, a second bus interface for interfacing with a second bus, and a mesh interface. Control logic is coupled to the first bus interface, the second bus interface and the mesh interface. The control logic includes circuitry for placing the interface circuit in a first mode in which a computc node resides on the first bus and a second mode in which the compute node resides on the second bus. The first bus may be a split-envelope bus such as the MIPS Avalanche bus. The second bus may be a single-envelope bus such as the PCI bus.
摘要翻译：用于将一个或多个计算节点连接到网格的接口电路能够服务于广泛的MPP系统。接口电路包括用于与第一总线接口的第一总线接口，用于与第二总线接口的第二总线接口和网格接口。控制逻辑耦合到第一总线接口，第二总线接口和网状接口。控制逻辑包括用于将接口电路放置在第一模式中的电路，其中计算节点驻留在第一总线上，以及计算节点驻留在第二总线上的第二模式。第一个总线可能是分裂信封的总线，如MIPS雪崩总线。第二总线可以是诸如PCI总线的单信封总线。

8. 发明授权

EP0875031B1 PROZESSOR ZUR BILDVERARBEITUNG 失效
标题翻译：处理器进行图像处理
公开(公告)号：EP0875031B1
公开(公告)日：2001-06-20
申请号：EP96946193.8
申请日：1996-12-13
申请人： Infineon Technologies AG
发明人： HACHMANN, Ulrich , RAAB, Wolfgang , SCHACKOW, Alexander , RAMACHER, Ulrich , SCHÜFFNY, Rene , BRÜLS, Nikolaus , GLIESE, Jörg
IPC分类号： G06F15/16
CPC分类号： G06F15/17337
摘要： The invention essentially concerns a matrix array of processor units, each processor unit having an arithmetic logic unit (ALU2) and a result-registering bank (REGF) as well as an additional arithmetic logic unit (ALU1), a multiplier/adder (MA), one storage unit (ISB) of a divided screen-section memory and a local general-purpose memory (GPM). The processor is characterized by its high data-processing speed for a small chip surface and makes real-time processing possible even with calculation-intensive image-processing techniques such as 2D-folding, Gabor transformation, Gauss or Laplace pyramids, block matching, DCT and MPEG2.

9. 发明授权

EP0882267B1 MEHRPROZESSOR-ZENTRALEINHEIT 失效
标题翻译：更多处理器控制单元
公开(公告)号：EP0882267B1
公开(公告)日：2000-04-26
申请号：EP97915275.8
申请日：1997-02-04
申请人： Siemens Nixdorf Informationssysteme AG
发明人： LUEDTKE, Harald
IPC分类号： G06F15/16
CPC分类号： G06F15/17337 , G06F12/0284 , G06F12/0607 , G06F12/0813 , G06F12/0817
摘要： The invention concerns central processing units having two or more groups each comprising a processor, a memory and a coupler, the processor and memory being interconnected by precisely one coupler and the couplers being interconnected. By interleaving addresses, a memory area uniformly distributed over the address space is associated disjunctively with each group. Each coupler carries out access to the memory area associated with its group itself and other accesses via the connection to the related coupler. The central processing units are provided with interfaces for constructing multiple systems.

10. 发明授权

EP0780775B1 Architecture d'un système de tableaux de processeurs à structures parallèles multiples 失效
标题翻译：阵列处理器的具有多个平行结构的系统的体系结构
公开(公告)号：EP0780775B1
公开(公告)日：2000-03-08
申请号：EP96402760.1
申请日：1996-12-17
申请人： COMMISSARIAT A L'ENERGIE ATOMIQUE
发明人： Essafi, Hassane , D'Humieres, Dominique , Pic, Marc
IPC分类号： G06F15/80 , G06F15/173
CPC分类号： G06F15/17337 , G06F15/8023

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