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1. 发明授权

EP3131015B1 MEMORY MIGRATION METHOD AND DEVICE 有权
公开(公告)号：EP3131015B1
公开(公告)日：2018-08-15
申请号：EP15840667.8
申请日：2015-06-01
申请人： Huawei Technologies Co., Ltd.
发明人： CHU, Lixing
IPC分类号： G06F12/06 , G06F12/0813 , G06F3/06 , G06F9/50
CPC分类号： G06F3/0647 , G06F3/06 , G06F3/0619 , G06F3/064 , G06F3/0644 , G06F3/0683 , G06F9/50 , G06F9/5016 , G06F9/5022 , G06F9/5033 , G06F12/06 , G06F12/0813 , G06F2212/2542
摘要： A memory migration method and device are provided, and relate to the field of computer application technologies. A memory page is combined into a memory block, which reduces a quantity of migrations, and improves CPU utilization. The method includes: receiving, by a first node, a migration instruction sent by a second node (201); sequentially scanning each memory page between a physical address of a start memory page accessed by a target process and a physical address of an end memory page accessed by the target process (202), where the memory page is a memory page accessed by the target process or a memory page accessed by a non-target process; determining whether each memory page meets a block combination condition, and combining a memory page that meets the block combination condition into a corresponding memory block (203); and migrating the corresponding memory block to a memory area of the second node (204).

2. 发明公开

EP2869208A4 METHOD FOR CONSTRUCTING MULTIPROCESSOR SYSTEM WITH NODE HAVING A PLURALITY OF CACHE UNIFORMITY DOMAINS 审中-公开
标题翻译：一种用于生产多处理器系统与多个缓存GLEICHFÖRMIGKEITSDOMÄNEN结
公开(公告)号：EP2869208A4
公开(公告)日：2016-04-20
申请号：EP13865541
申请日：2013-01-22
申请人： INSPUR ELECTRONIC INFORMATION INDUSTRY CO LTD
发明人： WANG ENDONG , HU LEIJUN , CHEN JICHENG , ZHANG DONG , GONG WEIFENG , ZHANG FENG
IPC分类号： G06F15/167 , G06F12/08 , G06F15/173
CPC分类号： G06F12/0822 , G06F12/082 , G06F12/0826 , G06F15/17368 , G06F2212/1016 , G06F2212/1048 , G06F2212/2542 , G06F2212/622

3. 发明公开

EP2664990A4 METHOD AND DEVICE FOR IMPLEMENTING MEMORY MIGRATION 审中-公开
标题翻译：方法和一种用于执行内存迁移
公开(公告)号：EP2664990A4
公开(公告)日：2014-01-22
申请号：EP11851937
申请日：2011-07-28
申请人： HUAWEI TECH CO LTD
发明人： QIU XISHI , WANG WEI , HAN GAOHUAI
IPC分类号： G06F9/50 , G06F9/48 , G06F11/20
CPC分类号： G06F3/0647 , G06F3/0619 , G06F3/067 , G06F9/485 , G06F11/1456 , G06F12/0292 , G06F2212/1032 , G06F2212/2542
摘要： Disclosed are a method and device for implementing memory migration, which relate to computer technology and are invented for solving the problem that the existing operating process for memory migration is relatively complicated. The technical solution provided in the embodiments of the present invention includes: the basic input-output system of a computer migrating the data in the memory to be migrated to a first unavailable memory in the operating system of the computer when migrating the memory to be migrated and the basic input-output system storing the mapping relationship between the memory to be migrated and the physical address of the first unavailable memory. The embodiments of the present invention can be applied to ordinary computer systems and computer systems under the NUMA architecture.

4. 发明公开

EP2664990A1 METHOD AND DEVICE FOR IMPLEMENTING MEMORY MIGRATION 审中-公开
标题翻译： VERFAHREN UND VORRICHTUNG ZUR DURCHFHHRUNG VON SPEICHERMIGRATION
公开(公告)号：EP2664990A1
公开(公告)日：2013-11-20
申请号：EP11851937.0
申请日：2011-07-28
申请人： Huawei Technologies Co., Ltd.
发明人： QIU, Xishi , WANG, Wei , HAN, Gaohuai
IPC分类号： G06F9/50
CPC分类号： G06F3/0647 , G06F3/0619 , G06F3/067 , G06F9/485 , G06F11/1456 , G06F12/0292 , G06F2212/1032 , G06F2212/2542
摘要： Disclosed are a method and device for implementing memory migration, which relate to computer technology and are invented for solving the problem that the existing operating process for memory migration is relatively complicated. The technical solution provided in the embodiments of the present invention includes: the basic input-output system of a computer migrating the data in the memory to be migrated to a first unavailable memory in the operating system of the computer when migrating the memory to be migrated and the basic input-output system storing the mapping relationship between the memory to be migrated and the physical address of the first unavailable memory. The embodiments of the present invention can be applied to ordinary computer systems and computer systems under the NUMA architecture.
摘要翻译：公开了一种用于实现与计算机技术相关的存储器迁移的方法和装置，并且被发明用于解决存储器迁移的现有操作过程相对复杂的问题。在本发明的实施例中提供的技术方案包括：当迁移要迁移的存储器时，计算机的操作系统中迁移到要移动的存储器中的数据迁移到第一不可用存储器的计算机的基本输入 - 输出系统以及存储要迁移的存储器与第一不可用存储器的物理地址之间的映射关系的基本输入 - 输出系统。本发明的实施例可以应用于NUMA架构下的普通计算机系统和计算机系统。

5. 发明公开

EP2411916A4 VIRTUAL NON-UNIFORM MEMORY ARCHITECTURE FOR VIRTUAL MACHINES 有权转让
标题翻译：虚拟内存结构虚拟机片状
公开(公告)号：EP2411916A4
公开(公告)日：2013-01-30
申请号：EP10756651
申请日：2010-03-19
申请人： MICROSOFT CORP
发明人： OSHINS JACOB
IPC分类号： G06F9/455 , G06F9/06 , G06F12/02 , G06F13/14
CPC分类号： G06F3/0631 , G06F3/0604 , G06F3/0665 , G06F3/0683 , G06F9/45504 , G06F9/45558 , G06F9/4856 , G06F9/5077 , G06F12/0284 , G06F2009/45562 , G06F2212/152 , G06F2212/2542
摘要： Techniques for effectuating a virtual NUMA architecture for virtual machines are disclosed herein. In an embodiment, a system determines the physical topology of a datacenter. When instantiating a virtual machine, the system determines a number of NUMA nodes for that VM based on the physical topology. The system then directs a second system to instantiate the virtual machine with the determined number of NUMA nodes.

6. 发明公开

EP2434402A2 METHOD AND DEVICE FOR MULTITHREAD TO ACCESS MULTIPLE COPIES 审中-公开
标题翻译：方法和装置一个多个线程访问多个副本
公开(公告)号：EP2434402A2
公开(公告)日：2012-03-28
申请号：EP11768473.8
申请日：2011-05-20
申请人： Huawei Technologies Co., Ltd.
发明人： WANG, Wei , LIU, Yiyang , ZHANG, Xiaofeng
IPC分类号： G06F9/46
CPC分类号： G06F12/1009 , G06F2212/2542
摘要： Embodiments of the present invention provide a method and a device for multithread to access multiple copies. The method includes: when multiple threads of a process are distributed to different nodes, creating a thread page directory table whose content is the same as that of a process page directory table of the process, where each thread page directory table includes a special entry, which points to specific data, and a common entry other than the special entry, each thread corresponds to a thread page directory table, execution of each thread is based on a corresponding thread page directory table, and the specific data is data with multiple copies at different nodes; and when each thread is scheduled and the special entry in the thread page directory table of the each thread does not point to the specific data stored in a node where the thread is located, modifying, based on a physical address of the specific data, the special entry to point to the specific data. Based on the technical solutions, the threads distributed to different nodes are enabled to access data copies stored in nodes where the threads are located, and thereby improving the system performance.

7. 发明公开

EP2224343A1 Data processing system 有权
标题翻译： Datenverarbeitungssystem
公开(公告)号：EP2224343A1
公开(公告)日：2010-09-01
申请号：EP10151912.2
申请日：2010-01-28
申请人： FUJITSU LIMITED
发明人： Sugizaki, Go
IPC分类号： G06F12/08 , G06F12/12
CPC分类号： G06F12/0811 , G06F12/12 , G06F2212/2542
摘要： A data processing system (100) includes a plurality of nodes (SB0, SB1, ... SB7) connected with each other, each of the nodes including a processor (CPU0, CPU1, .. CPU3) and a memory (MEMO, MEM1, .. MEM3), each of the processors including a processing unit (301), a cache memory (302, 304), a tag memory (306) for storing tag information, the processor accessing data to be processed, in the tag memory (306) in reference to the tag information, and a cache controller (310) for controlling saving or evacuating of data in the cache memory. The cache controller (310) checks if the data to be evacuated originated from the memory of its own node or from any other memory of any other node, and when the data to be evacuated originated from any other memory of any other node, stores the data into the memory of its own node at a particular address of the memory and stores information of the particular address in the tag memory (306) as tag information.
摘要翻译：数据处理系统（100）包括彼此连接的多个节点（SB0，SB1，... SB7），每个节点包括处理器（CPU0，CPU1，CPU3）和存储器（MEMO，MEM1 ，MEM3），每个处理器包括处理单元（301），高速缓冲存储器（302,304），用于存储标签信息的标签存储器（306），处理器访问待处理的数据，在标签存储器（306），以及用于控制高速缓冲存储器中的数据的保存或撤回的高速缓存控制器（310）。高速缓存控制器（310）检查要撤离的数据是否源自其自身节点的存储器或任何其他节点的任何其他存储器，并且当要撤离的数据源自任何其他节点的任何其他存储器时，将数据存入存储器的特定地址处的其自身节点的存储器中，并将该特定地址的信息存储在标签存储器（306）中作为标签信息。

8. 发明公开

EP1906313A1 Memory management in a shared memory system 有权转让
标题翻译：在einem gemeinsam genutzten Speichersystem的Speicherverwwung
公开(公告)号：EP1906313A1
公开(公告)日：2008-04-02
申请号：EP07004381.5
申请日：2007-03-02
申请人： Broadcom Corporation
发明人： Pong, Fong, c/o Broadcom Corporation
IPC分类号： G06F12/08
CPC分类号： G06F12/082 , G06F12/0813 , G06F2212/2542
摘要： Methods, systems and computer program products to maintain cache coherency in a System On Chip (SOC) which is part of a distributed shared memory system are described. A local SOC unit that includes a local controller and an on-chip memory is provided. In response to receiving a request from a remote controller of a remote SOC to access a memory location, the local controller determines whether the local SOC has exclusive ownership of the requested memory location, sends data from the memory location if the local SOC has exclusive ownership of the memory location and stores an entry in the on-chip memory that identifies the remote SOC as having requested data from the memory location. The entry specifies whether the request from the remote SOC is for exclusive ownership of the memory location. The entry also includes a field that identifies the remote SOC as the requester. The requested memory location may be external or internal to the local SOC unit.
摘要翻译：描述了作为分布式共享存储器系统的一部分的片上系统（SOC）中的高速缓存一致性的方法，系统和计算机程序产品。提供了包括本地控制器和片上存储器的本地SOC单元。响应于从远程SOC的远程控制器接收到访问存储器位置的请求，本地控制器确定本地SOC是否具有所请求的存储器位置的独占所有权，如果本地SOC具有专有所有权，则从存储器位置发送数据的存储器位置，并且将片段存储器中的条目存储，其将远程SOC识别为具有来自存储器位置的请求的数据。该条目指定来自远程SOC的请求是否用于存储器位置的专有所有权。该条目还包括将远程SOC识别为请求者的字段。请求的存储器位置可以是本地SOC单元的外部或内部。

9. 发明授权

EP0817076B1 A multiprocessing computer system employing local and global address spaces and multiple access modes 失效
标题翻译：多处理器计算机系统与本地和全局地址空间和多种接入方式
公开(公告)号：EP0817076B1
公开(公告)日：2003-08-27
申请号：EP97304652.7
申请日：1997-06-27
申请人： Sun Microsystems, Inc.
发明人： Hagersten, Erik E. , Loewenstein, Paul N.
IPC分类号： G06F12/08
CPC分类号： G06F12/0817 , G06F12/0284 , G06F12/0813 , G06F2212/2542 , G06F2212/272

10. 发明公开

EP1008940A2 Intelligent and adaptive memory and methods and devices for managing distributed memory systems with hardware-enforced coherency 审中-公开
标题翻译：智能和自适应存储器和用于分布式存储系统的管理方法和设备，硬件强制一致性
公开(公告)号：EP1008940A2
公开(公告)日：2000-06-14
申请号：EP99309343.4
申请日：1999-11-23
申请人： Network Virtual Systems Inc.
发明人： Akkawi, Isam , Donley, Greggory D. , Quinn, Robert F.
IPC分类号： G06F12/08
CPC分类号： G06F12/0817 , G06F12/0813 , G06F2212/2542 , G06F2212/507
摘要： Methods and devices for reducing memory access latencies in scaleable multi-node, multi-processor systems include supplementing the demand driven nature of filling cache memories wherein caches are filled based upon the past demands of the processor or processors coupled thereto with a push-based model wherein recently modified lines of memory are actively pushed into selected cache memories based upon usage information. The usage information is maintained for each line of memory and indicates at least which node in the system stores a copy of which line of memory. The timing of the pushing is adaptive and configurable and biases the system to push updated copies of recently modified lines of memory to selected nodes before the processors associated therewith request the line. Other methods and devices for reducing memory access latencies in a multi-node multi-processor system carry out the steps of generating two-phase acknowledgments to invalidate commands wherein, after a phase I acknowledgment, a requesting processor is allowed to modify a line of memory before other processors in the system receive the invalidate. A temporary and process-transparent incoherency then occurs for that line, which is resolved by delaying all access requests to the modified line until phase II acknowledgements to the invalidate are received from all nodes sharing that line. The push-based method of filling the cache memories may be employed together with the two phase invalidate acknowledgment method, or may be employed separately therefrom.
摘要翻译：方法和装置用于减少可扩展多节点的存储器访问等待时间，多处理器系统包括补充填充高速缓冲存储器worin高速缓存是基于与基于推送的模型耦合到其上的处理器的过去的要求或处理器填充的需求驱动性质 worin的存储器最近修改线被积极被推入基于使用信息选择的高速缓存存储器。该使用信息被保持的存储器中的每个线，并且指示至少哪个节点在系统存储的存储器，它线的拷贝。推压的定时是自适应的和可配置的和偏置系统有请求线相关联的处理器之前要推送的存储器最近修改的行更新的副本到选择的节点。用于降低多节点多处理器系统的存储器存取等待时间的其他方法和设备进行生成两相的确认的步骤，以无效命令worin，相位我确认之后，请求处理器被允许修改的线的存储器系统中的其它处理器之前收到无效。临时和过程透明不一致性则发生该线，所有这些通过延迟的所有访问请求被修改线，直到相位II确认到无效从所有节点共享做线路接收解决。填充所述高速缓冲存储器的基于推的方法可以连同两相无效确认方法中使用，或者可以从单独采用那里。

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