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81. 发明公开

EP2822184A1 Log-likelihood ratio (LLR) dampening in low-density parity-check (LDPC) decoders 有权
标题翻译：低密度奇偶校验（LDPC）解码器中的对数似然比（LLR）衰减
公开(公告)号：EP2822184A1
公开(公告)日：2015-01-07
申请号：EP14175629.6
申请日：2014-07-03
申请人： LSI Corporation
发明人： Cohen, Earl T. , Haratsch, Erich F. , Alhussien, Abdel-Hakim S.
IPC分类号： H03M13/37 , H03M13/11
CPC分类号： H03M13/618 , G06F11/1012 , H03M13/1111 , H03M13/1142 , H03M13/3723 , H03M13/6306 , H03M13/658 , H03M13/6591
摘要： Described embodiments provide a media controller to read data stored in a media. The media controller determines a value for each bit of a shortened codeword from the media. The shortened LDPC codeword includes a plurality of non-shortened bits of a full codeword, where the full codeword includes the plurality of non-shortened bits and one or more shortened bits. Shortened bits correspond to bits unused in the shortened codeword. The media controller converts the determined values for each bit of the shortened codeword into a first set of log-likelihood ratio (LLR) values. The full codeword is decoded using the first set of LLR values for the shortened codeword. If the LDPC decoding fails, the media controller dampens one or more LLR values corresponding to non-shortened bits of the codeword to produce a second set of LLR values and starts a second LDPC decoding trial using the second set of LLR values. The dampening of LLR values includes scaling by a predetermined scaling factor and decreasing their magnitude by a predetermined amount.
摘要翻译：所描述的实施例提供媒体控制器以读取存储在媒体中的数据。媒体控制器为来自媒体的缩短的码字的每个比特确定一个值。缩短的LDPC码字包括全码字的多个未缩短的比特，其中全码字包括多个未缩短的比特和一个或多个缩短的比特。缩短的比特对应于在缩短的码字中未使用的比特。媒体控制器将缩短码字的每个比特的确定值转换为第一组对数似然比（LLR）值。使用缩短的码字的第一组LLR值对全码字进行解码。如果LDPC解码失败，则媒体控制器衰减对应于码字的非缩短比特的一个或多个LLR值以产生第二组LLR值，并且使用第二组LLR值开始第二LDPC解码试验。 LLR值的衰减包括按预定缩放因子缩放并将其幅度减小预定量。

82. 发明公开

EP2779468A1 Min-sum based hybrid non-binary low-density parity check (LDPC) decoder 审中-公开
标题翻译：基于最小总和的混合非二进制低密度奇偶校验（LDPC）解码器
公开(公告)号：EP2779468A1
公开(公告)日：2014-09-17
申请号：EP14151571.8
申请日：2014-01-17
申请人： LSI Corporation
发明人： Wang, Chung-Li , Li, Zongwang , Li, Shu , Zhang, Fan , Yang, Shaohua
IPC分类号： H03M13/11
CPC分类号： H03M13/13 , H03M13/1122 , H03M13/1125 , H03M13/1171 , H03M13/6583
摘要： Systems, methods, devices, circuits for a min-sum based hybrid non-binary low density parity check decoder are disclosed. A data processing system (200) is disclosed including an apparatus for decoding data having a variable node processor (202) and a check node processor (204). The variable node processor is operable to generate variable node to check node messages and to calculate perceived values based on check node to variable node messages. The check node processor is operable to generate the check node to variable node messages and to calculate checksums based on variable node to check node messages. The variable node processor and the check node processor operate on different Galois fields GF(q) and GF(p), which requires transformations (242, 262) of the messages exchanged between the check and variable node processors from GF(q) to GF(p) and vice versa.
摘要翻译：公开了基于最小和的混合非二进制低密度奇偶校验解码器的系统，方法，设备和电路。公开了一种数据处理系统（200），其包括用于解码具有可变节点处理器（202）和校验节点处理器（204）的数据的设备。可变节点处理器可操作以生成变量节点以检查节点消息并且基于校验节点到变量节点消息来计算感知值。校验节点处理器可操作用于生成可变节点消息的校验节点并基于可变节点计算校验和以校验节点消息。变量节点处理器和校验节点处理器在不同的伽罗瓦域GF（q）和GF（p）上操作，这需要在检查和变量节点处理器之间从GF（q）到GF（j）交换的消息的变换（242,262）（p），反之亦然。

83. 发明公开

EP2778919A2 System, method and computer-readable medium for dynamic cache sharing in a flash-based caching solution supporting virtual machines 审中-公开
标题翻译：系统，方法和计算机可读介质用于在基于闪存的高速缓存解决方案动态地共享高速缓存使用的支持的虚拟机的
公开(公告)号：EP2778919A2
公开(公告)日：2014-09-17
申请号：EP14158960.6
申请日：2014-03-11
申请人： LSI Corporation
发明人： Venkatesha, Pradeep Radhakrishna , Panda, Siddhartha Kumar , Maharana, Parag , Bert, Luca
IPC分类号： G06F9/50 , G06F9/455 , G06F12/08
CPC分类号： G06F12/084 , G06F9/45558 , G06F9/5016 , G06F2009/45583 , G06F2212/222
摘要： A cache controller implemented in O/S kernel, driver and application levels within a guest virtual machine dynamically allocates a cache store to virtual machines for improved responsiveness to changing demands of virtual machines. A single cache device or a group of cache devices are provisioned as multiple logical devices and exposed to a resource allocator. A core caching algorithm executes in the guest virtual machine. As new virtual machines are added under the management of the virtual machine monitor, existing virtual machines are prompted to relinquish a portion of the cache store allocated for use by the respective existing machines. The relinquished cache is allocated to the new machine. Similarly, if a virtual machine is shutdown or migrated to a new host system, the cache capacity allocated to the virtual machine is redistributed among the remaining virtual machines being managed by the virtual machine monitor.
摘要翻译：一个客户虚拟机内的O / S的内核，驱动程序和应用级别上实现一个高速缓冲存储器控制器动态地分配一个高速缓存存储到虚拟机，以提高适应不断变化的虚拟机的需求。单个高速缓存设备或一组高速缓存装置被规定为多个逻辑设备，并暴露于资源分配器。核心缓存算法执行来宾虚拟机。作为新的虚拟机，虚拟机监视器的管理下，加入现有的虚拟机被提示放弃分配由respectivement现有的机器使用的缓存存储的一部分。该放弃缓存被分配到新机器。同样，如果一个虚拟机被关闭或迁移到新的主机系统，分配给虚拟机的高速缓存容量由虚拟机监视器被管理的剩余虚拟机之间重新分配。

84. 发明公开

EP2778890A2 Storage device assisted data de-duplication 审中-公开
标题翻译： SpeichervorrichtungsunterstützteDaten-entduplizierung
公开(公告)号：EP2778890A2
公开(公告)日：2014-09-17
申请号：EP14160056.9
申请日：2014-03-14
申请人： LSI Corporation
发明人： Cohen, Earl
IPC分类号： G06F3/06
CPC分类号： G06F3/0679 , G06F3/0608 , G06F3/0619 , G06F3/0641 , G06F3/0688
摘要： Systems and methods presented herein provide for de-duplication of data. In one embodiment (100), an input/output module (101) is operable to generate an input/output operation to write data. A storage device (102) is communicatively coupled to the input/output module and operable to write the data of the input/output operation at a logical address of the storage device, and to generate a signature based on the data. The input/output module is further operable to process the signature to determine whether the data exists at another logical address.
摘要翻译：本文提供的系统和方法提供数据的重复数据删除。在一个实施例（100）中，输入/输出模块（101）可操作以产生写入数据的输入/输出操作。存储设备（102）通信地耦合到输入/输出模块，并且可操作以将输入/输出操作的数据写入存储设备的逻辑地址，并且基于该数据生成签名。输入/输出模块还可操作以处理签名以确定数据是否存在于另一逻辑地址。

85. 发明公开

EP2767899A2 Non-volatile memory channel control using a general purpose programmable processor in combination with a low level programmable sequencer 审中-公开
标题翻译：组合使用可编程处理器与可编程序控制的低级别的非易失性存储器信道控制器
公开(公告)号：EP2767899A2
公开(公告)日：2014-08-20
申请号：EP14154095.5
申请日：2014-02-06
申请人： LSI Corporation
发明人： Brewer, Christopher , Cohen, Earl T.
IPC分类号： G06F9/38
CPC分类号： G06F3/0613 , G06F3/0659 , G06F3/0688 , G06F9/38 , G06F12/0246 , G06F13/1694 , G06F13/385 , G11C5/04
摘要： A system includes a control processor, a non-volatile memory device interface, and a micro-sequencer. The control processor may be configured to receive commands and send responses via a command interface. The non-volatile memory device interface may be configured to couple the system to one or more non-volatile memory devices. The micro-sequencer is generally coupled to (i) the control processor and (ii) the non-volatile memory device interface. The micro-sequencer includes a control store readable by the micro-sequencer and writable by the control processor. In response to receiving a particular one of the commands, the control processor is enabled to cause the micro-sequencer to begin executing at a location in the control store according to the particular command and the micro-sequencer is enabled to perform at least a portion of the particular command according to a protocol of the one or more non-volatile memory devices coupled to the non-volatile memory device interface.
摘要翻译：一种系统，包括：控制处理器，一个非易失性存储器设备接口，以及一微定序。控制处理器可以被配置成接收命令，并经由命令接口发送响应。非易失性存储器设备接口，可以在系统配置为耦合到一个或更多个非易失性存储器装置。微定序器是耦合到（i）所述控制处理器和（ii）所述非易失性存储器设备接口基因集会。微定序器包括一个控制存储由微定序器和可写的由控制处理器可读。响应于接收到的命令中的特定一个，被使能控制处理器，以使微定序到开始在控制存储雅丁到的特定命令和微定序器的位置执行能够执行至少一部分命令gemäß到耦合到所述非易失性存储器设备接口，所述一个或多个非易失性存储器装置的协议的特定。

86. 发明公开

EP2284650A3 Methods and apparatus for power allocation in a storage system 审中-公开
标题翻译：在存储系统的方法和用于功率分配装置
公开(公告)号：EP2284650A3
公开(公告)日：2014-08-13
申请号：EP10153419.6
申请日：2010-02-12
申请人： LSI Corporation
发明人： Day, Brian A. , Besmer, Brad D.
IPC分类号： G06F1/26
CPC分类号： G06F1/266
摘要： Methods and systems for improved management of power allocation among a plurality of devices coupled to a controller. The controller (102) and devices (106.1 .. 106.4) exchange messages to request, grant, and release allocations of power from a common power supply (108). In some embodiments, the controller may be a SAS/SATA controller and the messages exchanged may be SAS/SATA frames and/or primitives. In exemplary embodiments, the messages may request/grant a particular amount of power for each of one or more voltage levels provided by the power supply. In other exemplary embodiments, the messages may designate the duration of time during which the requesting device may utilize the allocated power. A power status message from the device to the controller may indicate a change in the power consumption by the device. Responsive to the power status message the controller may re-allocate power previously allocated to a device that has completed use thereof.

87. 发明公开

EP2706694A3 Apparatus and method for breaking trapping sets 审中-公开
标题翻译：装置和方法用于破坏捕获集
公开(公告)号：EP2706694A3
公开(公告)日：2014-08-06
申请号：EP13168975.4
申请日：2013-05-23
申请人： LSI Corporation
发明人： Han, Yang , Yang, Shaohua , Zhang, Fan , Li, Zongwang
IPC分类号： H04L1/00
CPC分类号： H03M13/6331 , H03M13/1142 , H03M13/2957 , H03M13/3723
摘要： An error correction data processing apparatus includes a noise predictive calibration circuit operable to calibrate a first set of filter coefficients based on a first data set and a second set of filter coefficients based on a second data set, and includes a first noise predictive detector operable to receive the first set of filter coefficients. The apparatus further includes a decoder operable to perform a first global iteration with the first noise predictive detector and determine a violation check count value, and a second noise predictive detector operable to receive the second set of filter coefficients if the violation check count value is less than a predetermined value or receive the first set of filter coefficients if the violation check count value is greater than the predetermined value.

88. 发明公开

EP2758896A1 VECTOR PROCESSOR HAVING INSTRUCTION SET WITH VECTOR CONVOLUTION FUNCITON FOR FIR FILTERING 审中-公开
标题翻译：与向量折叠功能FIR滤波命令系列矢量处理器
公开(公告)号：EP2758896A1
公开(公告)日：2014-07-30
申请号：EP12842890.1
申请日：2012-10-26
申请人： LSI Corporation
发明人： AZADET, Kameran , YU, Meng-lin , OTHMER, Joseph, H. , WILLIAMS, Joseph , MOLINA, Albert
IPC分类号： G06F17/16 , G06F9/06
CPC分类号： G06F9/3001 , G06F5/01 , G06F9/30036 , G06F17/15 , H03F1/0288 , H03F1/3241 , H03F1/3258 , H03F3/189 , H03F3/24 , H03F2200/336 , H03F2201/3209 , H03F2201/3212 , H03F2201/3224 , H03F2201/3233 , H03H17/06 , H03M3/30 , H04B1/0003 , H04B1/0475 , H04B1/62 , H04B2001/0408 , H04L1/0054 , H04L25/02 , H04L25/03 , H04L25/03178 , H04L25/03216 , H04L25/4917 , H04L27/2334
摘要： A vector processor is provided having an instruction set with a vector convolution function. The disclosed vector processor performs a convolution function between an input signal and a filter impulse response by obtaining a vector comprised of at least N1+N2-1 input samples; obtaining N2 time shifted versions of the vector (including a zero shifted version), wherein each time shifted version comprises N1 samples; and performing a weighted sum of the time shifted versions of the vector by a vector of N1 coefficients; and producing an output vector comprising one output value for each of the weighted sums. The vector processor performs the method, for example, in response to one or more vector convolution software instructions having a vector input. The vector can comprise a plurality of real or complex input samples and the filter impulse response can be expressed using a plurality of coefficients that are real or complex.

89. 发明公开

EP2757462A2 Hybrid hard disk drive having a flash storage processor 审中-公开
标题翻译： Hybriden-Festplattenlaufwerk mit einem Flashspeicherprozessor
公开(公告)号：EP2757462A2
公开(公告)日：2014-07-23
申请号：EP13197773.8
申请日：2013-12-17
申请人： LSI Corporation
发明人： Fisher, Daniel S. , Zaharris, Daniel
IPC分类号： G06F3/06
CPC分类号： G06F12/0246 , G06F3/0625 , G06F3/0634 , G06F3/0685 , Y02D10/154
摘要： An apparatus is described that is configured to control operations in a hybrid hard disk drive. In an implementation, the apparatus includes a hybrid flash storage processor connected to the host interface that is configured to communicatively couple a flash storage component and to a hard disk integrated circuit chip. The integrated circuit chip includes a read/write channel device configured to communicatively couple to a hard disk drive assembly and a hard disk drive controller operatively coupled to the read/write channel device. The hard disk drive controller is configured to operate the read/write channel device to store and to retrieve data on the hard disk drive assembly. The flash storage processor is configured to furnish a command to the integrated circuit chip when the command represents an instruction for accessing the hard disk drive assembly and is configured to access the flash storage component when the command represents an instruction for accessing the flash storage component.
摘要翻译：描述了被配置为控制混合硬盘驱动器中的操作的装置。在一个实现中，该装置包括连接到主机接口的混合闪存存储处理器，其被配置为通信地耦合闪存存储组件和硬盘集成电路芯片。集成电路芯片包括被配置为通信地耦合到硬盘驱动器组件的读/写通道器件和可操作地耦合到读/写通道器件的硬盘驱动器控制器。硬盘驱动器控制器被配置为操作读/写通道设备来存储和检索硬盘驱动器组件上的数据。闪存存储处理器被配置为当命令表示用于访问硬盘驱动器组件的指令时向集成电路芯片提供命令，并且当命令表示访问闪存存储组件的指令时，闪存存储处理器被配置为访问闪存存储组件。

90. 发明公开

EP2750288A1 Hybrid digital/analog power amplifier 审中-公开
标题翻译： Hybride Digital / Analog-Leistungsverstärker
公开(公告)号：EP2750288A1
公开(公告)日：2014-07-02
申请号：EP13199769.4
申请日：2013-12-30
申请人： LSI Corporation
发明人： Wilson, Ross S. , Abdelli, Said E. , Kiss, Peter , Azadet, Kameran , Laturell, Donald R. , Macdonald, James F.
IPC分类号： H03F3/189 , H03F3/217
CPC分类号： H03F3/38 , H03F3/189 , H03F3/217
摘要： The invention may be embodied in radio frequency power amplifier (RF-PA) predriver circuits employing a hybrid analog/digital RF architecture including a resynchronizing digital-to-analog convertor to drive an efficient high-power output stage suitable for driving standard high power amplifier (HPA) output devices. The hybrid analog/digital RF architecture retains the advantages of high digital content integration found in conventional Class-S architecture, while relaxing the performance requirements on the output transistors and on the bitstream generator. The resulting predriver circuit combines the VLSI integration benefits of digital designs with the extensibility to arbitrary output power levels characteristic of analog designs. The hybrid analog/digital driving circuit is well suited for use with analog and Class-S HPAs used in wireless communication systems, such as the Doherty type HPA.
摘要翻译：本发明可以体现在使用包括再同步数模转换器的混合模拟/数字RF架构的射频功率放大器（RF-PA）预驱动电路中，以驱动适于驱动标准高功率放大器的高效大功率输出级（HPA）输出设备。混合模拟/数字RF架构保留了在传统S类架构中发现的高数字内容集成的优点，同时放松了对输出晶体管和比特流发生器的性能要求。所得到的预驱动电路将数字设计的VLSI集成优势与模拟设计特有的任意输出功率电平的可扩展性相结合。混合模拟/数字驱动电路非常适用于无线通信系统中使用的模拟和Class-S HPA，例如Doherty型HPA。

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