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71. 发明公开

EP2215724A2 REDUCED-COMPLEXITY DECODING ALGORITHMS FOR TAIL-BITING CONVOLUTIONAL CODES 审中-公开
标题翻译：德克萨斯州立大学MIT GERINGERKOMPLEXITÄTFÜRTAIL-BITING-FALTUNGSKODES
公开(公告)号：EP2215724A2
公开(公告)日：2010-08-11
申请号：EP08841999.9
申请日：2008-10-20
申请人： Telefonaktiebolaget LM Ericsson (publ)
发明人： CHEN, Tsao-Tsen , TSAI, Shiau-He Shawn
IPC分类号： H03M13/39
CPC分类号： H03M13/3938 , H03M13/2996 , H03M13/413
摘要： A decoder is provided which is configured to operate upon an input encoded sequence using a wrap around Viterbi procedure, and a decoding method which employs the decoder. The decoder/method is configured to output a selected path as a decode sequence, and to avoid storing, for a current iteration of the wrap-around Viterbi procedure other than a first iteration, a best path up to the current iteration.
摘要翻译：提供了一种解码器，其被配置为使用包绕维特比程序的输入编码序列进行操作，以及采用解码器的解码方法。解码器/方法被配置为输出所选择的路径作为解码序列，并且为了避免在当前迭代之前存储直到当前迭代的最佳路径，对于除第一次迭代之外的环绕维特比过程的当前迭代。

72. 发明公开

EP2131502A2 Coding and Viterbi decoding for tail-biting convolutional codes 有权
标题翻译： Codierung und Viterbi-DecodierungfürTail-Biting-Faltungscodes
公开(公告)号：EP2131502A2
公开(公告)日：2009-12-09
申请号：EP09161920.5
申请日：2009-06-04
申请人： Panasonic Corporation
发明人： Seki, Yuta
IPC分类号： H03M13/41 , H03M13/23
CPC分类号： H03M13/3994 , H03M13/09 , H03M13/235 , H03M13/4123 , H03M13/413 , H03M13/6306 , H03M13/6312 , H03M13/6356 , H03M13/6525 , H04L1/0041 , H04L1/0059 , H04L1/0071 , H04L1/0072 , H04L1/1896
摘要： The coding apparatus, coding processing target sequence forming method and Viterbi decoding apparatus of the present invention can realize low delay processing with a minimum number of repetitive processing and suppress the degradation of the accuracy of decoding at the ends of a decoded sequence due to truncation error. In the coding apparatus mounted on the transmitting apparatus (100), a control information rearranging section (130) receives as input a control information sequence, in which a plurality of control information blocks are arranged in a predetermined order, and forms a coding processing target sequence by rearranging the order of the plurality of control information blocks to form an assembled sequence grouping control information blocks comprised of predictable bit sequences in the plurality of control information blocks, and to allocate the assembled sequence to a predetermined position in the control information sequence. Further , an encoding section (140) encodes the coding target sequence using the tail-biting convolutional coding scheme.
摘要翻译：本发明的编码装置，编码处理对象序列形成方法和维特比解码装置可以以最小数量的重复处理实现低延迟处理，并且抑制由于截断误差导致的解码序列的末尾的解码精度的劣化。在安装在发送装置（100）上的编码装置中，控制信息重排部（130）接收作为输入的控制信息序列，其中以预定顺序排列多个控制信息块，并形成编码处理对象通过重新排列多个控制信息块的顺序来形成由多个控制信息块中的可预测位序列构成的组合序列分组控制信息块，并将组合序列分配到控制信息序列中的预定位置。此外，编码部（140）使用尾巴卷积编码方式对编码对象序列进行编码。

73. 发明公开

EP2075919A2 Decoding apparatus and decoding method 审中-公开
标题翻译： Dekodierungsvorrichtung und Dekodierungsverfahren
公开(公告)号：EP2075919A2
公开(公告)日：2009-07-01
申请号：EP08021681.5
申请日：2008-12-12
申请人： NEC Electronics Corporation
发明人： Takanashi, Mitsunori
IPC分类号： H03M13/41
CPC分类号： H03M13/413 , H03M13/09 , H03M13/3753 , H03M13/4161
摘要： The decoding apparatus includes an ACS unit to execute an add-compare-select operation on encoded received data, and an error detector to detect whether there is an error in decoded data calculated based on the executed add-compare-select operation, and if there is an error in the decoded data, the ACS unit additionally executes the add-compare-select operation on the received data.
摘要翻译：解码装置包括对编码的接收数据执行加法比较选择操作的ACS单元和检测基于执行的加法比较选择操作计算的解码数据中是否存在错误的错误检测器，如果存在是解码数据中的错误，ACS单元另外对所接收的数据执行加法比较选择操作。

74. 发明授权

EP0920138B1 Method and system for decoding tailbiting convolution codes 有权
标题翻译：尾比特卷积解码的方法和系统
公开(公告)号：EP0920138B1
公开(公告)日：2006-10-11
申请号：EP98309627.2
申请日：1998-11-24
申请人： Nortel Networks Limited
发明人： Atallah, Isa Bisher
IPC分类号： H03M13/00
CPC分类号： H03M13/6508 , H03M13/23 , H03M13/413

75. 发明授权

EP0925661B1 A DECODING TECHNIQUE FOR TAIL BITING CODES 失效
标题翻译：解码程序“咬尾”码
公开(公告)号：EP0925661B1
公开(公告)日：2004-11-24
申请号：EP97938666.1
申请日：1997-09-08
申请人： Ericsson Inc.
发明人： KHAYRALLAH, Ali, S. , HASSAN, Amer
IPC分类号： H04L1/00 , H03M13/00
CPC分类号： H03M13/6502 , H03M13/4123 , H03M13/413 , H04L1/0054
摘要： A method for decoding encoded digital data. A decoder generates a replicated decoding trellis and performs some number Dmax of decoding operations using the replicated trellis. Each decoding pass is offset by some amount δ, and the results of each pass are stored and compared with prior results to generate a final output information sequence.

76. 发明公开

EP1237285A3 Trellis coded modulation tails 审中-公开
标题翻译：网格调制的扩展-kodierter
公开(公告)号：EP1237285A3
公开(公告)日：2004-11-10
申请号：EP02090064.3
申请日：2002-02-20
申请人： Broadcom Corporation
发明人： Karaoguz, Jeyhan
IPC分类号： H03M13/25 , H03M13/27 , H03M13/29
CPC分类号： H03M13/256 , H03M13/235 , H03M13/2903 , H03M13/4123 , H03M13/413 , H03M13/6505 , H04L2027/003 , H04L2027/0046 , H04L2027/0095
摘要： An encoder includes a state machine configured to generate a payloads as a function of a state machine output, and an interface configured to generate a tail as a function of a binary representation of the state machine output at the end of the payload generation. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or the meaning of the claims.

77. 发明授权

EP1049001B1 Arithmetic apparatus 失效
标题翻译：运算单元
公开(公告)号：EP1049001B1
公开(公告)日：2004-03-17
申请号：EP00113488.1
申请日：1993-09-28
申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
发明人： Asano, Nobuo , Uesugi, Mitsuru , Ishikawa, Toshihiro , Okamoto, Minoru
IPC分类号： G06F7/48 , G06F17/10 , H03M13/41
CPC分类号： H03M13/6502 , G06F17/10 , H03M13/3961 , H03M13/41 , H03M13/4107 , H03M13/413 , H03M13/4169 , H03M13/6505

78. 发明公开

EP1049001A1 Arithmetic apparatus 失效
标题翻译： ArithmetischesGerät
公开(公告)号：EP1049001A1
公开(公告)日：2000-11-02
申请号：EP00113488.1
申请日：1993-09-28
申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
发明人： Asano, Nobuo , Uesugi, Mitsuru , Ishikawa, Toshihiro , Okamoto, Minoru
IPC分类号： G06F7/48 , G06F17/10 , H03M13/41
CPC分类号： H03M13/6502 , G06F17/10 , H03M13/3961 , H03M13/41 , H03M13/4107 , H03M13/413 , H03M13/4169 , H03M13/6505
摘要： An arithmetic apparatus in which while data read out of a memory (1) is shifted by means of a barrel shifter (3) by a shift bit number designated by data standing for an output signal of an inverter (5), data standing for an output signal of the barrel shifter (3) is inputted to a shift register (4) to thereby perform Viterbi decoding at a high speed.
摘要翻译：一种运算装置，其中，通过由倒档器（5）的输出信号指定的数据指定的移位位数，利用桶形移位器（3）移位存储器（1）的数据，桶形移位器（3）的输出信号被输入到移位寄存器（4），从而以高速执行维特比解码。

79. 发明公开

EP0925661A1 A DECODING TECHNIQUE FOR TAIL BITING CODES 失效
标题翻译：解码程序“咬尾”码
公开(公告)号：EP0925661A1
公开(公告)日：1999-06-30
申请号：EP97938666.0
申请日：1997-09-08
申请人： ERICSSON INC.
发明人： KHAYRALLAH, Ali, S. , HASSAN, Amer
IPC分类号： H03M13 , H04L1 , H04L27
CPC分类号： H03M13/6502 , H03M13/4123 , H03M13/413 , H04L1/0054
摘要： A method for decoding encoded digital data. A decoder generates a replicated decoding trellis and performs some number Dmax of decoding operations using the replicated trellis. Each decoding pass is offset by some amount δ, and the results of each pass are stored and compared with prior results to generate a final output information sequence.

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