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71. 发明公开

EP1406268A3 Integrated circuit device with automatic internal command function 有权
标题翻译：带有自动的内部控制功能集成电路装置
公开(公告)号：EP1406268A3
公开(公告)日：2008-05-14
申请号：EP03027305.6
申请日：2001-04-30
申请人： FUJITSU LIMITED
发明人： Matsuzaki, Yasurou
IPC分类号： G11C11/406 , G11C11/4072
CPC分类号： G11C11/406 , G11C11/40603 , G11C11/40615 , G11C11/40618 , G11C11/4072 , G11C11/4094 , G11C2211/4061 , G11C2211/4065
摘要： An integrated circuit device has a first circuit (11) which receives commands (CMD) supplied in synchronization with a clock signal (CLK) and generates a first internal command (RD, WR) internally; a second circuit (20) which generates a second command (REF) internally, in a prescribed cycle longer than the cycles of said clock signal (CLK); and an internal circuit (14) which, according to said first internal command (RD, WR), executes corresponding control through clock-synchronous operations, and which, when said second command (REF) is issued, sequentially executes control corresponding to the second command and control corresponding to said first internal command through clock-asynchronous operations. For example, the integrated circuit is a DRAM having memory cells requiring a refresh operation, and the second command (REF) is a refresh command.

72. 发明公开

EP1876601A1 Procédé de rafraîchissement d'une mémoire vive dynamique, en particulier en mode veille et en mode de fonctionnement actif, et dispositif de mémoire vive dynamique correspondant, par exemple incorporé dans un téléphone mobile cellulaire 有权
标题翻译：刷新动态随机存取存储器，特别是在备用模式和运行的活动模式，以及适当的动态随机存取存储器装置中，例如所述的方法，集成在移动电话
公开(公告)号：EP1876601A1
公开(公告)日：2008-01-09
申请号：EP07111495.3
申请日：2007-07-02
申请人： STMicroelectronics SA
发明人： Harrand, Michel
IPC分类号： G11C11/406
CPC分类号： G11C11/406 , G11C11/40615 , G11C2211/4061 , G11C2211/4065 , G11C2211/4067
摘要： L'invention vise un une mémoire vive dynamique comprenant des groupes de cellules mémoire, ladite mémoire comprenant une mémoire auxiliaire par groupe de cellules, stockant des informations de rafraîchissement (SN, SR) spécifiques au groupe de cellules.
摘要翻译：该RAM具有用于从一组存储器单元，其中，所述刷新信息具有当前刷新周期，时间组的存储特定于一组存储单元的刷新信息的单个端口静态存储器剩余刷新之前，读访问指示和 WRITEACCESS指示。单端口静态存储器管理用于每个组unabhängig其他组的存储单元的刷新的信息。的逻辑电路更新指示取决于是否细胞的关联组被读取/期间写访问。因此独立claimsoft被包括为用于刷新动态RAM的方法。

73. 发明公开

EP1858024A1 Semiconductor memory and refresh cycle control method 有权
标题翻译： Halbleiterspeicher und Steuerungsverfahrenfürden Auffrischungszyklus
公开(公告)号：EP1858024A1
公开(公告)日：2007-11-21
申请号：EP07107117.9
申请日：2007-04-27
申请人： Fujitsu Ltd.
发明人： Mori, Kaoru
IPC分类号： G11C11/406
CPC分类号： G11C11/406 , G11C7/04 , G11C11/401 , G11C11/40626 , G11C29/02 , G11C29/028 , G11C2029/0409 , G11C2029/5002 , G11C2211/4061 , G11C2211/4067
摘要： A semiconductor memory and a refresh cycle control method that reduce a standby current by properly changing a refresh cycle according to the temperature of the semiconductor memory. A temperature detection section (101) detects the temperature of the semiconductor memory. A cycle change control section (102) sends a cycle change signal for changing a refresh cycle when the temperature of the semiconductor memory reaches a predetermined cycle change temperature. A refresh timing signal generation section (103) generates a refresh timing signal and changes the cycle of the refresh timing signal in response to the cycle change signal. A constant current generation circuit (104) generates an electric current for generating the refresh timing signal. A low-temperature constant current setting circuit (105) designates the level of the electric current generated in the case that the temperature of the semiconductor memory is lower than or equal to the cycle change temperature. A high-temperature constant current setting circuit (106) designates the level of the electric current generated in the case that the temperature of the semiconductor memory is higher than the cycle change temperature.
摘要翻译：一种半导体存储器和刷新周期控制方法，其通过根据半导体存储器的温度适当地改变刷新周期来减少待机电流。温度检测部（101）检测半导体存储器的温度。当半导体存储器的温度达到预定的周期变化温度时，循环变化控制部分（102）发送用于改变刷新周期的循环改变信号。刷新定时信号生成部（103）生成刷新定时信号，根据周期变更信号改变刷新定时信号的周期。恒定电流产生电路（104）产生用于产生刷新定时信号的电流。低温恒流设定电路（105）表示在半导体存储器的温度低于或等于循环变化温度的情况下产生的电流的电平。高温恒流设定电路（106）表示在半导体存储器的温度高于循环变化温度的情况下产生的电流的电平。

74. 发明公开

EP1815479A1 METHOD AND SYSTEM FOR MINIMIZING IMPACT OF REFRESH OPERATIONS ON VOLATILE MEMORY PERFORMANCE 有权
标题翻译：方法和系统最小化操作更新的影响在非挥发性内存的性能
公开(公告)号：EP1815479A1
公开(公告)日：2007-08-08
申请号：EP05824687.7
申请日：2005-11-22
申请人： Qualcomm Incorporated
发明人： WALKER, Robert, Michael
IPC分类号： G11C11/406
CPC分类号： G11C11/406 , G06F13/1636 , G11C11/40611 , G11C2211/4061
摘要： A memory system is provided. The system includes a volatile memory, a refresh counter configured to monitor a number of advanced refreshes performed in the volatile memory, and a controller configured to check the refresh counter to determine whether a regularly scheduled refresh can be skipped in response to detecting a request for the regularly scheduled refresh.

75. 发明公开

EP1734535A1 Semiconductor memory 有权
标题翻译：半导体内存
公开(公告)号：EP1734535A1
公开(公告)日：2006-12-20
申请号：EP05292248.1
申请日：2005-10-25
申请人： FUJITSU LIMITED
发明人： Okuyama, Yoshiaki, Fujitsu Limited
IPC分类号： G11C11/406
CPC分类号： G11C11/40603 , G11C11/406 , G11C11/40626 , G11C2211/4061 , G11C2211/4067
摘要： An oscillator generates a refresh request signal periodically. A storing circuit changes a stored value by a predetermined value in response to the refresh request signal and returns the stored value by one in response to a refresh operation. A store control circuit, when a state detecting circuit detects a change of an operational state of a semiconductor memory, increases or decreases the predetermined value which the storing circuit uses. A refresh decision circuit outputs refresh signals of a number corresponding to the stored value until the stored value returns to an initial value. This makes it possible to change the frequency of the refresh operations according to a change of the operational state without changing an oscillation cycle of the oscillator. Without unnecessary oscillation of the oscillator, it is possible to decrease a standby current of the semiconductor memory.
摘要翻译：振荡器周期性地产生刷新请求信号。存储电路响应于刷新请求信号将存储值改变预定值，并且响应于刷新操作将存储值返回1。当状态检测电路检测到半导体存储器的操作状态的改变时，存储控制电路增加或减少存储电路使用的预定值。刷新判定电路输出对应于存储值的数字的刷新信号，直到存储值返回到初始值。这使得可以在不改变振荡器的振荡周期的情况下根据操作状态的改变来改变刷新操作的频率。没有振荡器的不必要的振荡，可以降低半导体存储器的待机电流。

76. 发明公开

EP1671357A2 CIRCUIT AND METHOD FOR CONTROLLING A CLOCK SYNCHRONIZING CIRCUIT FOR LOW POWER REFRESH OPERATION 有权
标题翻译：电路和一种用于控制时钟同步电路，用于低功率刷新
公开(公告)号：EP1671357A2
公开(公告)日：2006-06-21
申请号：EP04789283.1
申请日：2004-09-29
申请人： MICRON TECHNOLOGY, INC.
发明人： SCHOENFELD, Aaron, M. , DERMOTT, Ross, E.
IPC分类号： H01L21/00
CPC分类号： G11C7/222 , G11C7/22 , G11C11/406 , G11C2211/4061 , G11C2211/4067
摘要： A method and apparatus is provided for idling a clock synchronizing circuit during at least a portion of time during execution of a refresh operation in a memory device. In a memory device receiving an external clock signal, a method and apparatus for executing a refresh operation is provided that includes initiating at least one refresh operation in the memory device, and ceasing generation of an internal clock signal timed with respect to the external clock signal for at least a portion of the time in which at least one refresh operation takes to complete.

77. 发明公开

EP1669999A1 Semiconductor memory 有权
标题翻译：半导体内存
公开(公告)号：EP1669999A1
公开(公告)日：2006-06-14
申请号：EP06004589.5
申请日：2003-02-20
申请人： FUJITSU LIMITED
发明人： Nakamura, Toshikazu c/o Fujitsu Limited , Eto, Satoshi c/o Fujitsu Limited , Miyo, Toshiya c/o Fujitsu Limited
IPC分类号： G11C11/401 , G11C11/4076
CPC分类号： G11C11/40603 , G11C7/22 , G11C11/401 , G11C11/406 , G11C11/40615 , G11C11/4076 , G11C29/02 , G11C29/022 , G11C29/028 , G11C29/50012 , G11C2207/2281 , G11C2211/4061
摘要： A semiconductor memory comprising; a memory core having a memory cell that requires a refresh for data retention; a refresh control circuit that generates at predetermined intervals a refresh command to refresh said memory cell; a sub state machine that issues a refresh permission, a read permission, and a write permission to operate said memory core, in accordance with the refresh command, and a read command and a write command supplied from exterior, respectively; and a main state machine that makes said memory core perform a refresh operation according to the refresh permission, perform a read operation according to the read permission, and perform a write operation according to the write permission, wherein: said sub state machine has a ready state and a reserve state, the ready state being a state to which the sub state machine makes a transition when no read command is supplied, the reserve state being a state to which the sub state machine makes a transition from the ready state in response to the read command; said main state machine has an idle state in which it puts said memory core in nonoperation, a read state in which it makes said memory core perform a read operation, a write state in which it makes said memory core perform a write operation, and a refresh state in which it makes said memory core perform a refresh operation.
摘要翻译：一种半导体存储器，具有存储器单元的存储器核心，所述存储器单元需要刷新以保持数据; 刷新控制电路，其以预定间隔产生刷新命令以刷新所述存储器单元; 子状态机，其根据所述刷新命令以及从外部分别提供的读取命令和写入命令来发出刷新许可，读取许可和写入许可以操作所述存储器核心; 以及主状态机，其使得所述存储器核根据所述刷新许可执行刷新操作，根据所述读取许可执行读取操作，并且根据所述写入许可执行写入操作，其中：所述子状态机具有就绪状态和备用状态，所述就绪状态是当没有读取命令被提供时所述副状态机进行转换的状态，所述备用状态是所述副状态机响应于所述备用状态从所述就绪状态转换到的状态读命令; 所述主状态机具有使所述存储器核处于非操作状态的空闲状态，使所述存储器核进行读取操作的读取状态，使所述存储器核进行写入操作的写入状态，以及刷新状态，其中它使所述存储器内核执行刷新操作。

78. 发明公开

EP1233419A3 Procédé de rafraîchissement d'une mémoire dynamique 审中-公开
标题翻译：动态存储器的重写方法
公开(公告)号：EP1233419A3
公开(公告)日：2006-04-19
申请号：EP02075562.5
申请日：2002-02-11
申请人： Koninklijke Philips Electronics N.V.
发明人： Duranton, Marc, Société Civile S.P.I.D
IPC分类号： G11C11/406
CPC分类号： G11C11/406 , G11C2211/4061
摘要： Un procédé de rafraîchissement d'une mémoire dynamique destinée à stocker des variables intervenant dans des opérations effectuées par un processeur comprend une étape d'ordonnancement 10 au cours de laquelle sont établis un ordre et un chronométrage des opérations, une étape d'estimation 13 d'un temps de rétention propre à chaque variable, une étape de prévision 14 d'au moins un instant auquel chaque variable doit être rafraîchie, une étape de placement 15 au cours de laquelle les variables sont placées dans la mémoire et une étape de rafraîchissement 16 au cours de laquelle les variables sont rafraîchies aux instants définis pendant l'étape de prévision 14. L'invention permet une réduction des temps de latence et de la consommation de courant liés au rafraîchissement. Elle présente notamment un intérêt dans des systèmes où la contrainte temps réel est importante, par exemple des systèmes de traitement de données vidéo.

79. 发明公开

EP1517332A4 SEMICONDUCTOR MEMORY 有权
标题翻译：半导体存储器
公开(公告)号：EP1517332A4
公开(公告)日：2005-09-14
申请号：EP03705345
申请日：2003-02-20
申请人： FUJITSU LTD
发明人： NAKAMURA TOSHIKAZU , ETO SATOSHI , MIYO TOSHIYA
IPC分类号： G11C7/22 , G11C11/406 , G11C11/4076 , G11C11/401
CPC分类号： G11C11/40603 , G11C7/22 , G11C11/401 , G11C11/406 , G11C11/40615 , G11C11/4076 , G11C29/02 , G11C29/022 , G11C29/028 , G11C29/50012 , G11C2207/2281 , G11C2211/4061
摘要： A timer begins to measure time, when receiving an external access signal for causing a memory core to execute a read operation, and outputs, after a predetermined time, an access request signal for activating the memory core. The predetermined time has been set to a time longer than the core operation time in which the memory core performs one operation. For this reason, when the external access signal changes in a time shorter than the predetermined time, the memory core will not operate. This can prevent malfunction of the memory core and hence prevent data stored in the memory cells from being destroyed even when the external access signals are supplied at such time intervals that do not allow the memory core to perform normal operations.

80. 发明公开

EP1542237A1 SEMICONDUCTOR MEMORY 审中-公开
标题翻译：半导体存储器
公开(公告)号：EP1542237A1
公开(公告)日：2005-06-15
申请号：EP02780005.1
申请日：2002-11-06
申请人： FUJITSU LIMITED
发明人： SHINOZAKI, Naoharu, c/o FUJITSU LIMITED , KANDA, Tatsuya, c/o FUJITSU LIMITED , SATO, Takahiko, c/o FUJITSU LIMITED , FUNYU, Akihiro, c/o FUJITSU LIMITED
IPC分类号： G11C11/401
CPC分类号： G11C29/028 , G11C11/401 , G11C11/406 , G11C11/40603 , G11C29/02 , G11C29/50012 , G11C29/50016 , G11C2029/0403 , G11C2211/4061
摘要： A refresh signal is output in response to a refresh request generated at predetermined cycles, and a refresh operation is performed. The refresh operation ends when a conflict occurs between an access request and the refresh request. Consequently, an access operation corresponding to the access request can be started earlier with a reduction in access time. The access time can be reduced further by changing the end time of the refresh operation in accordance with the timing of supply of the access request. Since a test circuit for notifying the state of the refresh operation to exterior is formed, the operation margin of the refresh operation can be evaluated in a short time. As a result, it is possible to reduce the development period of the semiconductor memory.
摘要翻译：响应于以预定周期产生的刷新请求输出刷新信号，并且执行刷新操作。刷新操作在访问请求和刷新请求之间发生冲突时结束。因此，与访问请求相对应的访问操作可以随着访问时间的减少而提前开始。通过根据提供访问请求的时间改变刷新操作的结束时间，可以进一步减少访问时间。由于形成了用于向外部通知刷新操作的状态的测试电路，所以可以在短时间内评估刷新操作的操作余量。结果，可以减少半导体存储器的开发周期。

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