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71. 发明授权

EP1835506B1 Semiconductor memory, memory system, and operation method of memory system 有权转让
标题翻译：半导体存储器，存储系统和操作方法，用于一存储系统的
公开(公告)号：EP1835506B1
公开(公告)日：2009-10-21
申请号：EP06115556.0
申请日：2006-06-15
申请人： Fujitsu Microelectronics Limited
发明人： Uchida, Toshiya c/o FUJITSU LIMITED
IPC分类号： G11C7/22 , G11C8/12
CPC分类号： G11C11/406 , G11C7/1051 , G11C7/1063 , G11C7/1072 , G11C8/12 , G11C11/40603 , G11C11/40615 , G11C11/40618 , G11C11/408 , G11C11/4096

72. 发明公开

EP2058819A1 Semiconductor memory device and memory system 审中-公开
标题翻译： Halbleiterspeichervorrichtung und Speichersystem
公开(公告)号：EP2058819A1
公开(公告)日：2009-05-13
申请号：EP09152787.9
申请日：2004-12-30
申请人： Fujitsu Microelectronics Limited
发明人： Fujioka, Shinya , Sato, Kotoku
IPC分类号： G11C11/406 , G11C7/22 , G11C7/10
CPC分类号： G11C11/406 , G11C7/1039 , G11C11/40603 , G11C11/40615
摘要： The semiconductor memory device of the present invention has a memory cell array with a plurality of memory cells disposed therein, a refresh request circuit outputting to an outside a refresh request signal requesting a refresh operation, a processing circuit decoding information relating to an external access request to the memory cell array, and instructing an operation to be executed in the memory cell array based on a decoded result, and an array control circuit executing an operation for the memory cell array based on an instruction from the processing circuit. The external access request includes a refresh execution request being a response to the refresh request signal.
摘要翻译：本发明的半导体存储器具具有设置在其中的多个存储单元的存储单元阵列，向外部向外部输出请求刷新动作的刷新请求信号的刷新请求电路，对外部访问请求进行解码的处理电路并且基于解码结果指示在存储单元阵列中执行的操作，以及基于来自处理电路的指令对存储单元阵列执行操作的阵列控制电路。外部访问请求包括作为对刷新请求信号的响应的刷新执行请求。

73. 发明授权

EP1840900B1 Dynamic semiconductor memory reducing the frequency of occurrence of refresh command request and refresh control method thereof 有权
标题翻译：与减少更新命令请求和更新控制方法的频率为此动态半导体存储器
公开(公告)号：EP1840900B1
公开(公告)日：2009-04-29
申请号：EP06115323.5
申请日：2006-06-12
申请人： Fujitsu Microelectronics Limited
发明人： Eto, Satoshi
IPC分类号： G11C11/406
CPC分类号： G11C11/406 , G11C11/40603 , G11C11/40618

74. 发明公开

EP2035934A2 DUAL-PORT SRAM MEMORY USING SINGLE-PORT MEMORY CELL 审中-公开
标题翻译：双端口SRAM内存单端口存储单元
公开(公告)号：EP2035934A2
公开(公告)日：2009-03-18
申请号：EP07811995.5
申请日：2007-06-01
申请人： MoSys, Inc.
发明人： LEUNG, Wingyu
IPC分类号： G06F12/00
CPC分类号： G11C7/1075 , G11C11/406 , G11C11/40603
摘要： A dual-port memory system is implemented using single-port memory cells. An access arbiter having a synchronization circuit is used to prioritize and synchronize the access requests associated with the two ports. The access arbiter can also prioritize and synchronize refresh requests, in the case where the single-port memory cells require refresh. Access requests on the two ports and the refresh requests can be asynchronous. The access arbiter synchronizes the various requests by latching the requests into first-stage registers when a row access signal (RAS) is activated, and subsequently latching the contents of the first-stage registers into second-stage registers after a selected delay.

75. 发明授权

EP1647028B1 1T1C SRAM 有权
公开(公告)号：EP1647028B1
公开(公告)日：2009-01-14
申请号：EP04778150.5
申请日：2004-07-14
申请人： ZMOS TECHNOLOGY, INC.
发明人： SOHN, Jeong-Duk
IPC分类号： G11C11/406
CPC分类号： G11C8/08 , G11C7/1021 , G11C11/406 , G11C11/40603 , G11C11/40615 , G11C11/40618 , G11C2207/2218 , G11C2211/4065
摘要： Memory circuits and methods are described providing an interface with high density dynamic memory (DRAM), such 1T1C (1 transistor and 1 capacitor) memory cells, providing full compatibility with static memory (SRAM). The circuitry overcomes the shortcomings with DRAM, such as associated with the restore and refresh operations, which have prevented full utilization of DRAM cores with SRAM compatible devices. The circuit can incorporate a number of inventive aspects, either singly or more preferably in combination, including a pulsed word line structure for limiting the maximum page mode cycle time, an address duration compare function with optional address buffering, and a late write function wherein the write operation commences after the write control signals are disabled.

76. 发明授权

EP1610342B1 Integrated circuit device with automatic internal command function 有权
标题翻译：具有自动内部命令功能电路部
公开(公告)号：EP1610342B1
公开(公告)日：2008-10-29
申请号：EP05018384.7
申请日：2001-04-30
申请人： FUJITSU LIMITED
发明人： Matsuzaki, Yasurou
IPC分类号： G11C11/406 , G11C11/4072
CPC分类号： G11C11/406 , G11C11/40603 , G11C11/40615 , G11C11/40618 , G11C11/4072 , G11C11/4094 , G11C2211/4061 , G11C2211/4065

77. 发明公开

EP1975941A1 Semiconductor memory, system, and operating method of semiconductor memory 有权
标题翻译： Halbleiterspeicher，系统和Betriebsverfahrenfürden Halbleiterspeicher
公开(公告)号：EP1975941A1
公开(公告)日：2008-10-01
申请号：EP08101064.7
申请日：2008-01-29
申请人： Fujitsu Ltd.
发明人： Tomita, Hiroyoshi c/o FUJITSU LIMITED
IPC分类号： G11C11/406
CPC分类号： G11C11/406 , G11C11/40603 , G11C11/40622 , G11C2211/4061
摘要： In a dynamic-type semiconductor memory such as a self-refresh type DRAM, partial refresh information indicating enabling/disabling of a refresh operation is set according to an external input (CAD) and is output as a partial set signal (PSET00, PSET01). A refresh request signal (RREQ0Z) is output periodically corresponding to a memory block (BLK0, BLK1 , ...)for which a refresh operation is enabled. The partial set signal is masked so as to enable a refresh operation for all of the memory blocks during a period in which the partial refresh information is changed by the external input. Thus, it is possible to prevent disabling of a refresh operation in response to a refresh request even when timing of changing the partial refresh information and timing of occurrence of the refresh request signal overlap. Consequently, the refresh operation can be executed securely, and malfunctioning of the semiconductor memory can be prevented.
摘要翻译：在诸如自刷新型DRAM的动态型半导体存储器中，根据外部输入（CAD）设定指示使能/禁止刷新操作的部分刷新信息，并作为部分设定信号（PSET00，PSET01）输出，。周期性地对与刷新操作启用的存储器块（BLK0，BLK1，...）相对应地输出刷新请求信号（RREQ0Z）。部分设置信号被屏蔽，以便在通过外部输入改变部分刷新信息的时段期间使得能够对所有存储器块进行刷新操作。因此，即使当改变部分刷新信息的定时和刷新请求信号的发生定时重叠时，也可以防止响应于刷新请求而禁止刷新操作。因此，可以可靠地执行刷新操作，并且可以防止半导体存储器的故障。

78. 发明公开

EP1970912A1 Semiconductor memory, memory controller, system, and operating method of semiconductor memory 有权
标题翻译： Halbleiterspeicher，Speichersteuerung，System und Betriebsverfahrenfüreinen Halbleiterspeicher
公开(公告)号：EP1970912A1
公开(公告)日：2008-09-17
申请号：EP08102051.3
申请日：2008-02-27
申请人： Fujitsu Ltd.
发明人： Kawabata, Kuninori
IPC分类号： G11C11/406
CPC分类号： G11C11/406 , G11C11/40603 , G11C11/40615
摘要： When a main block address held in a main refresh address counter (MRAC) coincides with an access block address corresponding to an access request, its counter value is transferred to a sub refresh address counter (SRAC). Thereafter, the sub refresh address counter (SRAC) operates with priority over the main refresh address counter (MRAC) until its counter value reaches a final value. Consequently, an access operation and a refresh operation can be simultaneously executed without interfering with each other. As a result, it is possible to execute the refresh operation with a minimum increase in circuit scale and without any deterioration in access efficiency.
摘要翻译：当保持在主刷新地址计数器（MRAC）中的主块地址与对应于访问请求的访问块地址一致时，其计数器值被传送到子刷新地址计数器（SRAC）。此后，子刷新地址计数器（SRAC）优先于主刷新地址计数器（MRAC）操作，直到其计数器值达到最终值。因此，可以同时执行访问操作和刷新操作而不会彼此干扰。结果，可以以最小的电路规模增加执行刷新操作，并且不会导致访问效率的降低。

79. 发明授权

EP1734535B1 Semiconductor memory 有权
公开(公告)号：EP1734535B1
公开(公告)日：2008-07-02
申请号：EP05292248.1
申请日：2005-10-25
申请人： FUJITSU LIMITED
发明人： Okuyama, Yoshiaki, Fujitsu Limited
IPC分类号： G11C11/406
CPC分类号： G11C11/40603 , G11C11/406 , G11C11/40626 , G11C2211/4061 , G11C2211/4067

80. 发明公开

EP1835506A1 Semiconductor memory, memory system, and operation method of memory system 有权转让
标题翻译： Halbleiterspeicher，Speichersystem und Betriebsverfahrenfürein Speichersystem
公开(公告)号：EP1835506A1
公开(公告)日：2007-09-19
申请号：EP06115556.0
申请日：2006-06-15
申请人： FUJITSU LIMITED
发明人： Uchida, Toshiya c/o FUJITSU LIMITED
IPC分类号： G11C7/22 , G11C8/12
CPC分类号： G11C11/406 , G11C7/1051 , G11C7/1063 , G11C7/1072 , G11C8/12 , G11C11/40603 , G11C11/40615 , G11C11/40618 , G11C11/408 , G11C11/4096
摘要： A memory system includes a semiconductor memory having a plurality of banks; and a controller accessing the semiconductor memory. The number of the banks is larger than the number of banks simultaneously accessed. When receiving an access command for the bank currently executing the access operation, the semiconductor memory activates a busy signal and keeps the busy signal active until the access operation currently executed is completed. The controller stops outputting a next access command while receiving the activated busy signal. Based on the received busy signal, the controller judges whether or not the next access command should be outputted to the semiconductor memory. Consequently, it is possible to easily execute the random access in a semiconductor memory having a plurality of banks, without giving any load to the system side, which can improve the data transfer rate at the time of the random access.
摘要翻译：存储器系统包括具有多个存储体的半导体存储器; 以及访问半导体存储器的控制器。银行数量大于同时访问的银行数量。当接收到当前执行访问操作的银行的访问命令时，半导体存储器激活忙信号并保持忙信号有效直到当前执行的访问操作完成。控制器在接收到激活的忙信号的同时停止输出下一个访问命令。根据收到的忙信号，控制器判断下一个存取命令是否应输出到半导体存储器。因此，可以容易地在具有多个存储体的半导体存储器中执行随机存取，而不会给系统侧带来任何负担，这可以提高随机存取时的数据传输速率。

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