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71. 发明公开

EP2776919A1 REDUCING HARDWARE COSTS FOR SUPPORTING MISS LOOKAHEAD 有权
标题翻译： REDUZIERUNG VON HARDWAREKOSTENZURUNTERSTÜTZUNGEINES FEHLGESCHLAGENEN VORGRIFFS
公开(公告)号：EP2776919A1
公开(公告)日：2014-09-17
申请号：EP12784387.8
申请日：2012-10-11
申请人： Oracle International Corporation
发明人： CHOU, Yuan, C. , MAHURIN, Eric, W.
IPC分类号： G06F9/38 , G06F9/30
CPC分类号： G06F9/3842 , G06F9/30127 , G06F9/383 , G06F9/3838 , G06F9/384 , G06F9/3851 , G06F9/3857 , G06F9/3859 , G06F9/3863 , G06F9/3865
摘要： The disclosed embodiments relate to a system that executes program instructions on a processor. During a normal-execution mode, the system issues instructions for execution in program order. Upon encountering an unresolved data dependency during execution of an instruction, the system speculatively executes subsequent instructions in a lookahead mode to prefetch future loads. When an instruction retires during the lookahead mode, a working register which serves as a destination register for the instruction is not copied to a corresponding architectural register. Instead the architectural register is marked as invalid. Note that by not updating architectural registers during lookahead mode, the system eliminates the need to checkpoint the architectural registers prior to entering lookahead mode.
摘要翻译：所公开的实施例涉及在处理器上执行程序指令的系统。在正常执行模式下，系统以程序顺序发出执行指令。在执行指令期间遇到未解决的数据依赖性时，系统以推测模式推测执行后续指令以预取未来负载。当在前瞻模式期间退出指令时，作为指令的目的地寄存器的工作寄存器不被复制到对应的架构寄存器。相反，架构寄存器被标记为无效。请注意，通过在查找模式期间不更新架构寄存器，系统在进入前瞻模式之前不需要对架构寄存器进行检查。

72. 发明公开

EP2761478A1 BI-DIRECTIONAL COPYING OF REGISTER CONTENT INTO SHADOW REGISTERS 审中-公开
标题翻译： TAB含量的影子寄存器双向COPY
公开(公告)号：EP2761478A1
公开(公告)日：2014-08-06
申请号：EP11873137.1
申请日：2011-09-29
申请人： Intel Corporation
发明人： WANG, Cheng , WU, Youfeng , CHUNG, Jaewoong
IPC分类号： G06F13/14 , G06F12/00 , G06F9/30
CPC分类号： G06F3/065 , G06F9/30116 , G06F9/30123 , G06F9/3863
摘要： Embodiments of the present disclosure describe a processor, which may include copy circuitry coupled to a shadow register file and a control register. The copy circuitry may be configured to copy content from a range of a number of registers to a shadow range of the shadow register file in a forward or backward direction. The forward or backward direction may be based at least in part on a value stored in the control register.

73. 发明公开

EP2619687A4 SHARING VIRTUAL FUNCTIONS IN A SHARED VIRTUAL MEMORY BETWEEN HETEROGENEOUS PROCESSORS OF A COMPUTING PLATFORM 有权转让
标题翻译：共享虚拟函数的具有计算机平台的异构处理器之间的接头虚拟存储器
公开(公告)号：EP2619687A4
公开(公告)日：2014-04-09
申请号：EP10857421
申请日：2010-09-24
申请人： INTEL CORP
发明人： YAN SHOUMENG , LUO SAI , ZHOU XIAOCHENG , GAO YING , CHEN HU , SAHA BRATIN
IPC分类号： G06F15/167 , G06F9/54
CPC分类号： G06F12/1072 , G06F8/447 , G06F9/3863 , G06F9/3885 , G06F9/548 , G06F2212/657

74. 发明公开

EP2613251A1 Restoring a register renaming map 有权转让
标题翻译： Wiederherstellung einer Registerumbenennsksk
公开(公告)号：EP2613251A1
公开(公告)日：2013-07-10
申请号：EP12196230.2
申请日：2012-12-10
申请人： Imagination Technologies Limited
发明人： Jackson, Hugh
IPC分类号： G06F9/38
CPC分类号： G06F9/30043 , G06F9/3836 , G06F9/384 , G06F9/3855 , G06F9/3857 , G06F9/3863
摘要： A technique for restoring a register renaming map is described. In one example, a restore table having a number of storage locations saves a copy of the register renaming map whenever a flow-risk instruction is passed to a re-order buffer. When all storage locations are full, further instructions still pass to the re-order buffer, but a copy of the map is not saved. A storage location subsequently becomes available when its associated flow-risk instruction is executed. A register renaming map state for an unrecorded flow-risk instruction passed to the re-order buffer whilst the storage locations were full is generated and stored in the available location. This is generated using the restore table entry for a previous flow-risk instruction and re-order buffer values for intervening instructions between the previous and unrecorded flow-risk instructions. The restore table can be used to restore the map if an unexpected change in instruction flow occurs.
摘要翻译：描述了恢复寄存器重命名映射的技术。在一个示例中，具有多个存储位置的恢复表每当流程风险指令被传递到重新排序缓冲器时，都保存了重命名映射映射的副本。当所有存储位置都已满时，进一步的指令仍然传递给重新排序缓冲区，但是映射的副本不会被保存。当其相关联的流程风险指令被执行时，存储位置随后变得可用。在存储位置已满的情况下，生成并存储在可用位置中存储传递到重新排序缓冲器的未记录流量风险指令的寄存器重命名映射状态。这是使用恢复表条目为先前的流程风险指令生成的，并重新排序缓冲区值，用于在先前和未记录的流量风险指令之间进行干预指令。如果发生意外的指令流程更改，还原表可用于恢复映射。

75. 发明授权

EP1296230B1 Instruction issuing in the presence of load misses 有权
标题翻译：在充电失误的存在命令输出
公开(公告)号：EP1296230B1
公开(公告)日：2011-02-09
申请号：EP02021394.8
申请日：2002-09-24
申请人： Broadcom Corporation
发明人： Yeh, Tse-Yu
IPC分类号： G06F9/38
CPC分类号： G06F9/3842 , G06F9/30065 , G06F9/3826 , G06F9/3836 , G06F9/3838 , G06F9/3863 , G06F9/3867

76. 发明公开

EP2054799A2 REGISTER WITH A CONTEXT SWITCH DEVICE AND METHOD OF CONTEXT SWITCHING 审中-公开
标题翻译：登记手续情境改变情境改变的系统和方法
公开(公告)号：EP2054799A2
公开(公告)日：2009-05-06
申请号：EP07799980.3
申请日：2007-08-02
申请人： QUALCOMM Incorporated
发明人： LIN, Jentsung , KUO, Eai-hsin Alfred , HSU, De Dzwo
IPC分类号： G06F9/30
CPC分类号： G06F9/30123 , G01R31/31853 , G01R31/318533 , G06F9/30116 , G06F9/30141 , G06F9/3863 , G06F9/462
摘要： A method of changing execution contexts is provided that includes receiving a context selection input. In a first clock phase, the method includes shifting data from a first latch element of a normal execution context to a second latch element of the normal execution context and shifting shadow data from a third latch element of a shadow execution context to a fourth latch element of the shadow execution context. In a second clock phase, the method includes shifting the shadow data of the fourth latch element of the shadow execution context into the first latch element of the normal execution context and shifting the data of the second latch element of the normal execution context into the third latch element of the shadow execution context. In a particular embodiment, the method may include receiving a test mode selection and shifting test data, such as scan test or automatic test pattern generated data, to a test output.

77. 发明公开

EP1999575A2 METHOD AND APPARATUS FOR SIMULTANEOUS SPECULATIVE THREADING 有权转让
标题翻译： VERFAHREN UND VORRICHTUNGFÜR同时进行SPEKULATIVES螺纹
公开(公告)号：EP1999575A2
公开(公告)日：2008-12-10
申请号：EP07717177.5
申请日：2007-02-02
申请人： SUN MICROSYSTEMS, INC.
发明人： CHAUDHRY, Shailender , TREMBLAY, Marc , CAPRIOLI, Paul
IPC分类号： G06F9/38
CPC分类号： G06F9/3851 , G06F9/383 , G06F9/3842 , G06F9/3863
摘要： One embodiment of the present invention provides a system which performs simultaneous speculative threading. The system starts by executing instructions in normal execution mode using a first thread. Upon encountering a data-dependent stall condition, the first thread generates an architectural checkpoint and commences execution of instructions in execute-ahead mode. During execute-ahead mode, the first thread executes instructions that can be executed and defers instructions that cannot be executed into a deferred queue. When the data dependent stall condition has been resolved, the first thread generates a speculative checkpoint and continues execution in execute-ahead mode. At the same time, the second thread commences execution in a deferred mode, wherein the second thread executes instructions deferred by the first thread.
摘要翻译：本发明的一个实施例提供一种执行同时投机线程的系统。系统通过使用第一个线程在正常执行模式下执行指令来启动。在遇到数据相关的停顿状态时，第一个线程生成一个架构检查点，并以执行提前模式开始执行指令。在执行提前模式期间，第一个线程执行可执行的指令，并将不能执行的指令拖放到延迟队列中。当数据相关失速条件已经解决时，第一个线程生成一个推测检查点，并以执行提前模式继续执行。同时，第二个线程以延迟模式开始执行。在延迟模式执行期间，第二线程执行由第一线程延迟的指令。

78. 发明公开

EP1984814A2 METHOD AND APPARATUS FOR ENFORCING MEMORY REFERENCE ORDERING REQUIREMENTS AT THE L1 CACHE LEVEL 有权转让
标题翻译：方法和装置强迫内存的引用规则，要求在L1高速缓存级别
公开(公告)号：EP1984814A2
公开(公告)日：2008-10-29
申请号：EP07717171.8
申请日：2007-02-02
申请人： SUN MICROSYSTEMS, INC.
发明人： CHAUDHRY, Shailender , TREMBLAY, Marc
IPC分类号： G06F9/38
CPC分类号： G06F9/3834 , G06F9/30189 , G06F9/3842 , G06F9/3863
摘要： One embodiment of the present invention provides a system that enforces memory reference ordering requirements, such as Total Store Ordering (TSO), at a Level 1 (L1) cache in a multiprocessor. During operation, while executing instructions in a speculative-execution mode, the system receives an invalidation signal for a cache line at the L1 cache wherein the invalidation signal is received from a cache-coherence system within the multiprocessor. In response to the invalidation signal, if the cache line exists in the L1 cache, the system examines a load-mark in the cache line, wherein the load-mark being set indicates that the cache line has been loaded from during speculative execution. If the load-mark is set, the system fails the speculative-execution mode and resumes a normal-execution mode from a checkpoint. By failing the speculative-execution mode, the system ensures that a potential update to the cache line indicated by the invalidation signal will not cause the memory reference ordering requirements to be violated during the speculative-execution mode.

79. 发明公开

EP1973036A2 Efficient and consistent software transactional memory 审中-公开
标题翻译：高效，一致的软件事务内存
公开(公告)号：EP1973036A2
公开(公告)日：2008-09-24
申请号：EP07254932.2
申请日：2007-12-18
申请人： Intel Corporation
发明人： Saha, Bratin , Adl-Tabatabai, Ali-Reza , Wang, Cheng , Wu, Youfeng , Chen, Wei-Yu
IPC分类号： G06F9/46 , G06F9/38
CPC分类号： G06F8/458 , G06F9/3004 , G06F9/30087 , G06F9/3834 , G06F9/3859 , G06F9/3863 , G06F9/467
摘要： A method and apparatus for efficient and consistent validation/conflict detection in a Software Transactional Memory (STM) system is herein described. A version check barrier is inserted after a load to compare versions of loaded values before and after the load. In addition, a global timestamp (GTS) is utilized to track a latest committed transaction. Each transaction is associated with a local timestamp (LTS) initialized to the GTS value at the start of a transaction. As a transaction commits it updates the GTS to a new value and sets versions of modified locations to the new value. Pending transactions compare versions determined in read barriers to their LTS. If the version is greater than their LTS indicating another transaction has committed after the pending transaction started and initialized the LTS, then the pending transaction validates its read set to maintain efficient and consistent transactional execution.

80. 发明公开

EP1618476A2 PROGRAMMGESTEUERTE EINHEIT UND VERFAHREN 审中-公开
标题翻译：程控单元和方法
公开(公告)号：EP1618476A2
公开(公告)日：2006-01-25
申请号：EP04741455.2
申请日：2004-04-07
申请人： ROBERT BOSCH GMBH
发明人： WEIBERLE, Reinhard , BOEHL, Eberhard , KOTTKE, Thomas
IPC分类号： G06F11/16
CPC分类号： G06F9/3001 , G06F9/30105 , G06F9/30116 , G06F9/30189 , G06F9/3836 , G06F9/3863 , G06F9/3885 , G06F11/1641
摘要： The invention relates to a program-controlled unit comprising a single controller core provided with a first and at least one second execution unit that can be independently operated in a first operating mode and execute the same commands in parallel in a second operating mode.

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