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61. 发明公开

EP2327282A4 ADDITIONAL FUNCTIONALITY SINGLE LAMMINATION STACKED VIA WITH PLATED THROUGH HOLES FOR MULTILAYER PRINTED CIRCUIT BOARDS 有权
标题翻译：与微孔堆叠式镀存款通过孔，用于多层电路板与附加功能
公开(公告)号：EP2327282A4
公开(公告)日：2015-10-14
申请号：EP09807322
申请日：2009-08-13
申请人： VIASYSTEMS TECHNOLOGIES CORP L L C
发明人： KUMAR RAJ , DREYER MONTE , TAYLOR MICHAEL J , ZEPEDA RUBEN
IPC分类号： H05K1/11 , H05K1/03 , H05K3/38 , H05K3/40 , H05K3/42 , H05K3/46
CPC分类号： H05K3/4614 , H05K3/386 , H05K3/4069 , H05K3/427 , H05K3/429 , H05K3/462 , H05K3/4623 , H05K2201/0195 , H05K2201/0352 , H05K2201/09454 , H05K2201/09563 , H05K2201/096 , H05K2201/09736 , H05K2201/09845 , H05K2203/0191 , H05K2203/0554 , H05K2203/061 , H05K2203/1152 , Y10T29/49128 , Y10T29/49156 , Y10T29/49165

62. 发明公开

EP2896279A1 VERFAHREN ZUM HERSTELLEN EINER IN EINEM SUBSTRAT INTEGRIERTEN ODER AUF EINEM SUBSTRAT AUFGEBRACHTEN SPULE UND ELEKTRONISCHES GERÄT 审中-公开
标题翻译：方法用于在集成或在基底上，应用卷曲和电子器件用基板
公开(公告)号：EP2896279A1
公开(公告)日：2015-07-22
申请号：EP13771409.3
申请日：2013-09-12
申请人： Würth Elektronik GmbH & Co. KG , Festo AG & Co. KG
发明人： KOSTELNICK, Jan , SCHREIVOGEL, Alina , KIESSLING, Albert , GIOUSOUF, Metin
IPC分类号： H05K1/16 , H01F5/00 , H05K3/46 , H03K17/95
CPC分类号： H01F27/2804 , H01F17/0006 , H01F27/2823 , H01F27/324 , H01F41/046 , H01F41/06 , H01F2017/002 , H01F2017/0066 , H01F2027/406 , H03K17/9505 , H05K1/165 , H05K3/4623 , H05K2201/086 , H05K2201/09036 , H05K2203/061 , Y10T29/49073
摘要： The invention relates to a method for producing a coil (140) integrated in a substrate (100), comprising the following steps: producing a cavity in the substrate, which cavity has an open side, which interrupts a surface of the substrate, introducing a paste having ferromagnetic particles into the cavity in order to produce a coil core, closing the cavity by applying a cover layer in order to bridge the interruption of the surface of the substrate, introducing first winding segments of the coil which are perpendicular to the surface, wherein several or all of the first winding segments extend through the coil core located in the cavity, and applying second winding segments to the surfaces of the substrate, wherein the second winding segments contact the first winding segments in order to realize the windings of the coil.

63. 发明授权

EP2348579B1 Tile sub-array and related circuits and techniques 有权
标题翻译：板天线子阵列和相关联的电路和技术
公开(公告)号：EP2348579B1
公开(公告)日：2014-10-15
申请号：EP10188251.2
申请日：2007-07-31
申请人： RAYTHEON COMPANY
发明人： Puzella, Angelo M. , Crowder, Joseph M. , Dupuis, Patricia S. , Fallica, Michael C. , Francis, John B. , Licciardello, Joseph A.
IPC分类号： H01Q21/00
CPC分类号： H01Q21/0087 , H03H7/38 , H05K1/0251 , H05K1/116 , H05K3/429 , H05K3/4623 , H05K2201/09145 , H05K2201/09454 , H05K2201/09536 , H05K2201/09718 , H05K2201/09727 , H05K2201/209 , H05K2203/061 , Y10T29/49165

64. 发明公开

EP2775808A1 METHOD FOR MANUFACTURING SUBSTRATE HAVING BUILT-IN COMPONENT, AND SUBSTRATE HAVING BUILT-IN COMPONENT MANUFACTURED USING SAME 审中-公开
标题翻译：方法制造具有集成部件的基板，并与集成器件这种方法制成的衬底
公开(公告)号：EP2775808A1
公开(公告)日：2014-09-10
申请号：EP11874961.3
申请日：2011-10-31
申请人： Meiko Electronics Co., Ltd.
发明人： SHIMIZU, Ryoichi , MATSUMOTO, Tohru , HASEGAWA, Takuya , IMAMURA, Yoshio
IPC分类号： H05K3/46
CPC分类号： H05K3/4038 , H01L21/568 , H01L21/6835 , H01L23/544 , H01L24/19 , H01L24/27 , H01L24/29 , H01L24/32 , H01L24/82 , H01L24/83 , H01L24/92 , H01L2221/68359 , H01L2223/54426 , H01L2223/54486 , H01L2224/04105 , H01L2224/2741 , H01L2224/27436 , H01L2224/2919 , H01L2224/2929 , H01L2224/29387 , H01L2224/32245 , H01L2224/82039 , H01L2224/82132 , H01L2224/83005 , H01L2224/83132 , H01L2224/8314 , H01L2224/83192 , H01L2224/92144 , H01L2924/14 , H05K1/0266 , H05K1/0269 , H05K1/115 , H05K1/118 , H05K1/188 , H05K3/303 , H05K3/421 , H05K3/4602 , H05K3/4623 , H05K3/4652 , H05K2201/09063 , H05K2201/09918 , H05K2203/063 , H05K2203/0703 , H05K2203/1461 , Y02P70/613 , Y10T29/49165
摘要： The method includes the steps of: positioning an electronic component (14) using main marks (A and B) formed on a metal layer (4) as references and mounting the electronic component (14) on a second surface (5) of the metal layer (4) with an adhesive layer (18) interposed between the metal layer (4) and both of the electronic component (14) and terminals (20); then burying the electronic component (14) and the main marks (A and B) in an insulating substrate (34); then removing part of the metal layer (4) and forming a first window (W1) for exposing the main marks (A and B) therefrom and a second window (W2) for exposing the adhesive layer (18) including a position corresponding to the terminal (20) therefrom; then determining the position of the terminal (20) using the exposed main marks (A and B) as references and forming a laser via hole LVH (46) reaching the terminal (20) in the adhesive layer (18) exposed from the second window (W2); and thereby forming a wiring pattern (50) from the metal layer (4) electrically connected to the terminal (20) through a first conductive via (47) formed by plating the LVH (46) with copper.
摘要翻译：该方法包括以下步骤：在第二表面上使用形成的金属层（4）为基准对主标记（A和B）和安装电子部件（14）的电子部件（14）的定位（5）的金属层（4）与所述金属层之间插入粘合剂层（18）（4）和两个电子元件（14）和端子（20）的; 然后埋入在绝缘（34），所述电子部件（14）和主标记（A和B）的底物; 然后去除金属层（4）的一部分，并且从和第二窗口（W2），用于暴露包括对应于一个位置的粘接层（18）形成用于暴露所述主标记（A和B）一个第一窗口（W1）有终端（20）有从; 然后确定性采矿终端的使用暴露的主标记（A和B）作为参考并形成通孔LVH（46）的激光到达在粘合剂层中的端子（20）（18）从所述第二窗口露出的位置（20）（W2）; 并由此形成从通过第一导电金属层（4）电连接到所述终端（20）经由通过与铜电镀LVH（46）形成的布线图案（50）（47）。

65. 发明公开

EP2753159A1 LAMINATED SINTERED CERAMIC WIRING SUBSTRATE, AND SEMICONDUCTOR PACKAGE CONTAINING WIRING SUBSTRATE 审中-公开
标题翻译： LAMINIERTES GESINTERTERS KERAMISCHES VERDRAHTUNGSSUBSTRAT UND HALBLEITERPAKET MIT DEM VERDRAHTUNGSSUBSTRAT
公开(公告)号：EP2753159A1
公开(公告)日：2014-07-09
申请号：EP11871755.2
申请日：2011-08-29
申请人： NGK Insulators, Ltd.
发明人： TANI, Makoto , HIRAI, Takami , YANO, Shinsuke , TANABE, Daishi
IPC分类号： H05K3/46
CPC分类号： H05K3/4629 , H01L23/49822 , H01L23/49838 , H01L23/5283 , H01L2924/0002 , H05K1/0242 , H05K3/4623 , H05K2201/09227 , H05K2201/09236 , H05K2201/098 , H05K2201/09827 , H01L2924/00
摘要： In the laminated and sintered ceramic circuit board according to the present invention, at least a portion of the inplane conductor is fine-lined. Nevertheless, as described above, by means of the configuration that the shape of the cross-section of the fine-lined inplane conductor is trapezoid, and the height (a), the length (c) of the lower base and the length (d) of the upper base of the trapezoidal cross-section, and the interval (b) between the lower bases of the trapezoidal cross-section of the inplane conductors adjacent in a plane parallel to the principal surfaces of the board meet a certain relation, problems such as frequent occurrences of open of wiring (disconnection) and decrease in reliability under high temperature and high humidity environment can be suppressed. Namely, the present invention provides a laminated ceramic circuit board with low open failure rate, short-circuit failure rate and high reliability against high temperature and high humidity, in spite of its fine-lined wiring layer. In addition, the present invention provides a fast, downsized and short-in-height (thin) semiconductor package with high reliability by using such a circuit board.
摘要翻译：在根据本发明的层压和烧结陶瓷电路板中，面内导体的至少一部分是精细的。然而，如上所述，通过以下结构，细线面内导体的截面形状为梯形，高度（a），下基板的长度（c）和长度（d ）和梯形截面的上基部之间的间隔（b）与平行于板的主面的平面相邻的面内导体的梯形截面的下基座之间的间隔（b）满足一定关系，问题可以抑制在高温高湿环境下频繁发生布线（断开）和可靠性的降低。也就是说，本发明提供了一种具有低开路故障率，短路故障率和高温高湿可靠性的层压陶瓷电路板，尽管其精细布线层。此外，本发明通过使用这样的电路板提供了具有高可靠性的快速，小型化和高度低（薄）的半导体封装。

66. 发明授权

EP2346310B1 Multilayer wiring circuit board 有权
公开(公告)号：EP2346310B1
公开(公告)日：2012-12-05
申请号：EP11161217.2
申请日：2002-09-26
申请人： FUJITSU LIMITED
发明人： Kusagaya, Toshihiro , Yoneda, Yasuhiro , Mizutani, Daisuke , Iijima, Kazuhiko , Suwa, Yuji
IPC分类号： H05K3/46 , H05K1/02
CPC分类号： H05K3/4641 , H01L2224/05568 , H01L2224/05573 , H01L2224/16225 , H01L2924/01087 , H05K1/0216 , H05K1/113 , H05K3/0035 , H05K3/4602 , H05K3/4623 , H05K3/4626 , H05K3/4652 , H05K3/4655 , H05K3/4688 , H05K2201/0129 , H05K2201/0154 , H05K2201/09309 , H05K2201/09518 , H05K2201/09536 , H05K2201/096 , H05K2203/1394

68. 发明公开

EP2381752A4 MULTILAYER WIRING SUBSTRATE, AND METHOD FOR PRODUCING MULTILAYER WIRING SUBSTRATE 审中-公开
标题翻译：多层布线基板及其制造方法的多层布线基板
公开(公告)号：EP2381752A4
公开(公告)日：2012-01-18
申请号：EP11728763
申请日：2011-02-22
申请人： PANASONIC CORP
发明人： HIMORI TSUYOCHI , HIRAI SHOGO , ISHITOMI HIROYUKI , TOMEKAWA SATORU , NAKAYAMA YUTAKA
IPC分类号： H05K3/46 , H05K1/09 , H05K3/40
CPC分类号： H05K3/4069 , H05K3/4623 , H05K3/4626 , H05K2201/0195 , H05K2201/0272 , H05K2203/0425

69. 发明公开

EP2200414A3 Integrated circuit package 审中-公开
标题翻译：集成电路封装
公开(公告)号：EP2200414A3
公开(公告)日：2011-10-26
申请号：EP09252601.1
申请日：2009-11-11
申请人： Thales Holdings UK Plc
发明人： Loiselet, Emmanuel
IPC分类号： H05K3/46 , H01L23/10
CPC分类号： H01L21/50 , H01L23/10 , H01L23/3677 , H01L23/49816 , H01L23/49833 , H01L2224/48091 , H01L2224/48227 , H01L2924/01079 , H01L2924/09701 , H01L2924/15311 , H05K1/0206 , H05K1/0306 , H05K3/244 , H05K3/328 , H05K3/462 , H05K3/4623 , H05K3/4629 , H05K2201/0379 , H05K2203/1147 , H01L2924/00014
摘要： An integrated circuit package comprising at least two printed circuit boards each comprising a substrate coated with metallic layers on both sides and having plated through-holes for electrical and thermal connection to the metallic layers, at least two of the printed circuit boards being diffusion-bonded at an interface between their respective metallic layers, the bonded metallic layers forming an hermetic seal between the opposed external surfaces of the integrated circuit package.

70. 发明公开

EP2327282A1 ADDITIONAL FUNCTIONALITY SINGLE LAMMINATION STACKED VIA WITH PLATED THROUGH HOLES FOR MULTILAYER PRINTED CIRCUIT BOARDS 有权
标题翻译：与微孔堆叠式镀存款通过孔，用于多层电路板与附加功能
公开(公告)号：EP2327282A1
公开(公告)日：2011-06-01
申请号：EP09807322.4
申请日：2009-08-13
申请人： Dynamic Details, Inc.
发明人： KUMAR, Raj , DREYER, Monte , TAYLOR, Michael, J. , ZEPEDA, Ruben
IPC分类号： H05K1/11 , H05K1/03
CPC分类号： H05K3/4614 , H05K3/386 , H05K3/4069 , H05K3/427 , H05K3/429 , H05K3/462 , H05K3/4623 , H05K2201/0195 , H05K2201/0352 , H05K2201/09454 , H05K2201/09563 , H05K2201/096 , H05K2201/09736 , H05K2201/09845 , H05K2203/0191 , H05K2203/0554 , H05K2203/061 , H05K2203/1152 , Y10T29/49128 , Y10T29/49156 , Y10T29/49165
摘要： Methods of manufacturing at least a portion of a printed circuit board. The circuit board is formed to include a plurality of sub-assemblies, each of the sub-assemblies including a plurality of circuit layers and having at least one countersink and at least one hole, the countersink having a first diameter and a first depth from a first side of at least one of the sub-assemblies and into the at least one sub-assembly, the hole having a second diameter smaller than the first diameter and a second depth longer than the first depth from the first side of the at least one sub-assembly and into the at least one sub-assembly at the countersink; a metal metalized within the hole and the countersink; a lamination adhesive interposed between one and a corresponding one of the sub-assemblies and having at least one via formed there through; and a counter paste filled within the via.

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