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61. 发明公开

EP1201066A1 PHASE NOISE AND ADDITIVE NOISE ESTIMATION IN A QAM CARRIER RECOVERY CIRCUIT 有权
标题翻译： PHASE和层状噪声的甲QAM载波恢复电路估计
公开(公告)号：EP1201066A1
公开(公告)日：2002-05-02
申请号：EP01909286.5
申请日：2001-02-15
申请人： ATMEL CORPORATION
发明人： MAALEJ, Khaled , HAMMAN, Emmanuel , DEMOL, Amaury , LEVY, Yannick
IPC分类号： H04L27/38
CPC分类号： H04L27/3809 , H04L1/0057 , H04L1/0071 , H04L7/0029 , H04L27/3827 , H04L27/3872 , H04L2027/0032 , H04L2027/0036 , H04L2027/0038 , H04L2027/0055 , H04L2027/0057 , H04L2027/0071 , H04L2027/0081
摘要： A QAM demodulator having a carrier recovery circuit (50) that includes a phase estimation circuit (506) and an additive noise estimation circuit (507) which produces an estimation of the residual phase noise (518) and additive noise (519) viewed by the QAM demodulator. The phase noise estimation (518) is based on the least mean square error (512) between the QAM symbol (509) decided by a symbol decision circuit (508) and the received QAM symbol (504). The additive noise estimation is based on the same error as in the phase noise estimation (518), except that it is based only on QAM symbols having the minimum amplitude on the I and Q coordinates. The additive noise estimation (519) is not dependent on the phase of the signal, thus, is independent of the phase noise estimator.

62. 发明公开

EP1047235A1 CARRIER PHASE ESTIMATOR DEVICE AND DEMODULATOR 审中-公开
标题翻译：载波相位和预测DEMODULATOR
公开(公告)号：EP1047235A1
公开(公告)日：2000-10-25
申请号：EP99922526.1
申请日：1999-05-27
申请人： MITSUBISHI DENKI KABUSHIKI KAISHA
发明人： FUJIMURA, A., Mitsubishi Denki Kabushiki Kaisha , KOJIMA, T., Mitsubishi Denki Kabushiki Kaisha
IPC分类号： H04L27/22
CPC分类号： H04L27/227 , H04L2027/0048 , H04L2027/0067 , H04L2027/0073 , H04L2027/0081
摘要： A carrier phase estimation apparatus comprises a non-linear processor (20) which removes a modulated component from a received baseband signal to obtain a non-modulated complex data, a first moving average computing unit (25a) which computes a moving average of the non-modulated complex data, a carrier phase computing unit (24) which computes a carrier phase from a vector angle represented by the moving average, and a filter band computing unit (5) which controls a band of the first moving average computing unit (25a) by using data for r symbol in the past of the non-modulated complex data.

63. 发明公开

EP0966819A1 PHASE-LOCKED LOOP WITH CONTINUOUSLY ADJUSTABLE BANDWITH 失效
标题翻译：连续可调带宽相回路
公开(公告)号：EP0966819A1
公开(公告)日：1999-12-29
申请号：EP98910290.0
申请日：1998-03-11
申请人： INTERDIGITAL TECHNOLOGY CORPORATION
发明人： MESECHER, David, K. , YANG, Rui , CERDA, Ram(RTM)n
IPC分类号： H04L27 , H04B1 , H04B7
CPC分类号： H04B1/7085 , H04B1/707 , H04B1/7117 , H04L27/0014 , H04L27/2332 , H04L2027/0053 , H04L2027/0055 , H04L2027/0069 , H04L2027/0081
摘要： A continuously adjusted bandwidth phase-locked loop is used by a B-CDMATM receiver to correct for any deviation, or offset, that may exist between the received radio frequency (RF) carrier signal and the frequency of the first stage LO that converts the received RF carrier signal to an intermediate frequency (IF). The PLL in the receiver includes a filter with an adjustable bandwith. A wider bandwidth is used during initial acquisition of the received signal. After the PLL has acquired the received carrier signal using the wider bandwidth, the bandwidth of the filter is gradually narrowed to provide a low steady-state error.

64. 发明公开

EP0748124A3 Signal processing apparatus and method 失效
标题翻译：一种信号处理装置和方法
公开(公告)号：EP0748124A3
公开(公告)日：1999-05-06
申请号：EP96301869.2
申请日：1996-03-19
申请人： DISCOVISION ASSOCIATES
发明人： Claydon, Anthony P.J. , Macfarlane, Charles D. , Gammack, Richard J. , Jones, Anthony M. , Robbins, William P. , Barnes, Mark
IPC分类号： H04N7/52 , H04N7/60 , H04Q11/02
CPC分类号： H04L1/0057 , H03K5/24 , H03M13/15 , H03M13/151 , H03M13/2707 , H03M13/2764 , H04L1/0045 , H04L1/0071 , H04L7/0334 , H04L25/03038 , H04L25/03866 , H04L25/062 , H04L27/02 , H04L27/2273 , H04L27/3809 , H04L2027/0032 , H04L2027/0061 , H04L2027/0067 , H04L2027/0073 , H04L2027/0081 , H04N5/211 , H04N5/4401 , H04N5/4446 , H04N5/455 , H04N5/52
摘要： An integrated digital communication system utilizing multilevel vestigial sideband transmission is provided. The communication system receives a multi-level pulse-amplitude modulated digital signal from a limited bandwidth channel. The system includes processing stages which demodulate, sample and filter the incoming signal prior to recovery of the digital data. Other stages recover the timing and lock on to the frequency and phase of the transmitted signal, as well as provide for automatic gain control. An adaptive equalizer, error correction circuitry, and an output interface recover the digital data and provide for transfer to other devices.

65. 发明公开

EP0649237A1 AFC circuit for QPSK demodulator 失效
标题翻译： AFC-Schaltungfüreinen QPSK-Demodulator。
公开(公告)号：EP0649237A1
公开(公告)日：1995-04-19
申请号：EP94306801.5
申请日：1994-09-16
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Taga, Noboru, c/o Intellectual Property Division , Ishikawa, Tatsuya, c/o Intellectual Property Div. , Komatsu, Susumu, c/o Intellectual Property Div.
IPC分类号： H04L27/22
CPC分类号： H04L27/2332 , H04L2027/0032 , H04L2027/0055 , H04L2027/0057 , H04L2027/0065 , H04L2027/0081
摘要： AFC circuit for QPSK demodulator including, a circuit for obtaining quadrature related detection signals by multiplying a modulated input signal with quadrature related local oscillation frequency signals from a quadrature phase local oscillator, digital converter for converting the detection signals into corresponding digital signals by sampling them with quadrature related clocks which have a frequency two times higher than a symbol rate of the input signal, frequency error detecter for detecting a frequency error between the quadrature related digital signals using a symbol timing sample value and a symbol intermediate timing sample value in the converted digital signals, first validity determinator for determining whether the frequency error signal is valid or not through a detection of the pattern of the modulated input signal from sample values before and after the symbol timing so as to result a first validity signal, second validity determinator for deetermining whether the frequency error signal is valid or not through a detection of an absolute sample value of the symbol intermediate timing so as to result a second validity signal, and valid frequency error extractor for extracting the frequency error signal as a frequency control signal for controlling the oscillation frequency of the local oscillator when the frequency error signal has been proved to be valid by the first and the second validity signals.
摘要翻译：用于QPSK解调器的AFC电路，包括：通过将调制输入信号与来自正交相位本地振荡器的正交相关本地振荡频率信号相乘获得正交相关检测信号的电路，用于通过对检测信号进行采样将检测信号转换成相应的数字信号，具有比输入信号的符号率高两倍的频率的正交相关时钟，用于使用符号定时采样值检测正交相关数字信号之间的频率误差的频率误差检测器和转换后的数字信号中的符号中间定时采样值信号，第一有效性确定器，用于通过从符号定时之前和之后的采样值检测调制输入信号来确定频率误差信号是否有效，以产生第一有效信号，第二有效性确定器用于确定无论是通过检测符号中间定时的绝对采样值来产生第一有效信号，以及用于提取频率误差信号的有效频率误差提取器作为用于控制振荡频率的频率控制信号，当频率误差信号被证明是有效的第一和第二有效信号时的本地振荡器。

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