会员体验
专利管家（专利管理）
工作空间（专利管理）
风险监控（情报监控）
数据分析（专利分析）
侵权分析（诉讼无效）
联系我们
交流群
官方交流：
QQ群： 891211   
微信请扫码    >>>
现在联系顾问~
下载
著录项
PDF全文
热词
    • 56. 发明公开
      EP0043943A3 Method for forming field effect transistor integrated circuits having a pattern of narrow dimensioned dielectric regions and resulting structures 失效
    • Method for forming field effect transistor integrated circuits having a pattern of narrow dimensioned dielectric regions and resulting structures
    • 形成具有窄尺寸电介质区域和结构结构图案的场效应晶体管集成电路的方法
    • EP0043943A3
    • 1983-01-26
    • EP81104805
    • 1981-06-23
    • International Business Machines Corporation
    • Abbas, Shakir Ahmed , Magdo, Ingrid Emese
    • H01L21/28 , H01L21/31 , H01L21/00
    • H01L27/10844 , H01L21/0334 , H01L21/0337 , H01L21/321 , H01L29/41 , H01L29/41783 , H01L29/66537 , H01L29/66545 , H01L29/66553 , H01L29/66575 , H01L29/66583 , H01L29/66606 , H01L29/66621 , H01L2924/0002 , H01L2924/00
    • method for forming field effect transistor integrated circuits having a pattern of narrow dimensioned dielectric regions and more particularly a self-aligned metal process is described which achieves self-aligned metal to silicon contacts and submicron contact-to-contact and metal-to-metal spacing for field effect transistor integrated circuits. The insulation between the contacts and the metal is a pattern of dielectric material having a thickness dimension in the order of a micron or less. The metal and dielectric structure is substantially planar. The method for forming integrated circuits with this structure involves providing a silicon body (10) and then forming a first insulating layer (14) on a major surface of the silicon body. A layer of polycrystalline silicon (16) is formed thereover. Openings are made in the polycrystalline silicon layer by reactive ion etching which results in the structure having substantially horizontal surfaces (20) and substantially vertical surfaces (21). The openings can be in either the areas designated to be the gate regions or a PN junction region of the field effect transistors in the integrated circuit. A second insulating layer (22) is then formed on both the substantially horizontal surfaces (20) and substantially vertical surfaces (21). Reactive ion etching of this second insulating layer substantially removes the horizontal layers and provides a narrow dimensioned dielectric pattern of regions (22) on the major surface of the silicon body (10). The gate dielectric is either formed hereat or PN junctions are fabricated by diffusion or ion implantation techniques. The remaining polycrystalline silicon layer (16) is then removed by etching to leave the narrow dimensioned regions (22) on the major surface of the silicon body (10). A conductive layer is blanket deposited over the narrow dimensioned regions and areas in between to make contact to source;drain PN regions and form the gate electrodes. A blanker layer of a plastic material over the conductive layer is used to planarize the surface. Reactive ion etching the plastic material and the conductive layer is continued until the tops of the narrow dimensioned regions are reached leaving the structure of patterns of metal or polycrystalline silicon filling the regions between the pattern of dielectric material having having a thickness dimension in the order of a micron or less. The gate, source and drain electrodes are thusly formed.
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 57. 发明公开
      EP0043943A2 Method for forming field effect transistor integrated circuits having a pattern of narrow dimensioned dielectric regions and resulting structures 失效
    • Method for forming field effect transistor integrated circuits having a pattern of narrow dimensioned dielectric regions and resulting structures
    • 一种用于制造包括具有与由该方法生产的窄尺寸和结构的电介质区域的图案的场效应晶体管的集成电路的方法。
    • EP0043943A2
    • 1982-01-20
    • EP81104805.7
    • 1981-06-23
    • International Business Machines Corporation
    • Abbas, Shakir Ahmed , Magdo, Ingrid Emese
    • H01L21/28 , H01L21/31 , H01L21/00
    • H01L27/10844 , H01L21/0334 , H01L21/0337 , H01L21/321 , H01L29/41 , H01L29/41783 , H01L29/66537 , H01L29/66545 , H01L29/66553 , H01L29/66575 , H01L29/66583 , H01L29/66606 , H01L29/66621 , H01L2924/0002 , H01L2924/00
    • method for forming field effect transistor integrated circuits having a pattern of narrow dimensioned dielectric regions and more particularly a self-aligned metal process is described which achieves self-aligned metal to silicon contacts and submicron contact-to-contact and metal-to-metal spacing for field effect transistor integrated circuits. The insulation between the contacts and the metal is a pattern of dielectric material having a thickness dimension in the order of a micron or less. The metal and dielectric structure is substantially planar. The method for forming integrated circuits with this structure involves providing a silicon body (10) and then forming a first insulating layer (14) on a major surface of the silicon body. A layer of polycrystalline silicon (16) is formed thereover. Openings are made in the polycrystalline silicon layer by reactive ion etching which results in the structure having substantially horizontal surfaces (20) and substantially vertical surfaces (21). The openings can be in either the areas designated to be the gate regions or a PN junction region of the field effect transistors in the integrated circuit. A second insulating layer (22) is then formed on both the substantially horizontal surfaces (20) and substantially vertical surfaces (21). Reactive ion etching of this second insulating layer substantially removes the horizontal layers and provides a narrow dimensioned dielectric pattern of regions (22) on the major surface of the silicon body (10). The gate dielectric is either formed hereat or PN junctions are fabricated by diffusion or ion implantation techniques. The remaining polycrystalline silicon layer (16) is then removed by etching to leave the narrow dimensioned regions (22) on the major surface of the silicon body (10). A conductive layer is blanket deposited over the narrow dimensioned regions and areas in between to make contact to source;drain PN regions and form the gate electrodes. A blanker layer of a plastic material over the conductive layer is used to planarize the surface. Reactive ion etching the plastic material and the conductive layer is continued until the tops of the narrow dimensioned regions are reached leaving the structure of patterns of metal or polycrystalline silicon filling the regions between the pattern of dielectric material having having a thickness dimension in the order of a micron or less. The gate, source and drain electrodes are thusly formed.
    • 一种用于形成具有狭窄尺寸的电介质区域的图案和场效应晶体管的集成电路的方法更具体地自对准金属过程被描述其实现自对准金属硅接触和亚微米接触到接触和金属 - 金属 间距场效应晶体管的集成电路。 触点与金属之间的绝缘是具有一微米或更小的数量级的厚度尺寸的介电材料的图案。 的金属和电介质结构是基本平坦的。 用于形成具有这种结构的集成电路的方法，包括提供硅体（10），然后形成在硅主体的主表面上的第一绝缘层（14）。 多晶硅（16）的层上形成在那里。 开口中通过反应离子蚀刻，这导致结构具有基本上水平的表面（20）和基本垂直的表面（21）的多晶硅层制成。 开口可以是在任一指定为栅极区或在集成电路中的场效应晶体管的PN结区域的区域。 然后，第二绝缘层（22）形成在两个基本水平的表面（20）和基本垂直的表面（21）。 该第二绝缘层的反应离子蚀刻去除基本上水平层，并且提供一个窄尺寸的电介质区域上的硅体（10）的主表面图案（22）。 栅极电介质或者是于此形成，或者PN结是通过扩散或离子注入技术制造。 剩余的多晶硅层（16）然后，通过蚀刻到离开窄尺寸的区域（22）上的硅体（10）的主表面除去。 导电层是毯式沉积在窄尺寸的区域和区域之间进行接触到源极漏极区域的PN并且形成栅电极。 塑料材料在所述导电层的平滑层是用来使表面平坦化。 继续反应离子蚀刻所述塑料材料和导电层直到窄尺寸的区域的顶部被达到离开的填充具有在顺序具有厚度尺寸的介电材料的图案之间的区域的金属或多晶硅图案的结构 一微米或更小。 栅极，源极和漏极电极是这样形成的。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
每页展示10个专利
每页展示10个专利
每页展示20个专利
每页展示50个专利
每页展示100个专利

IPRDB

最新中国发明专利 最新美国发明专利 技术领域 专利库 专利分类库 国际专利分类库

热门服务

会员版试用 API 数据接口 找代理 知嘟嘟专利交易 排行榜 大学排行榜 专利百科

关于我们

平台介绍 战略合作 网站地图

友情链接

知嘟嘟专利交易 国家知识产权局 中国商标网

联系方式


©2019-2023 上海吉码数字技术有限公司 版权所有，并保留所有权利 沪ICP备20016256号-6 沪公网安备31011702005475号