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51. 发明公开

EP0552445A3 Field effect transistor 失效
标题翻译：场效应晶体管
公开(公告)号：EP0552445A3
公开(公告)日：1994-01-05
申请号：EP92120593.6
申请日：1992-12-02
申请人： MITSUBISHI DENKI KABUSHIKI KAISHA
发明人： Tsutsumi, Kazuhito, c/o Mitsubishi Denki K.K. LSI
IPC分类号： H01L29/772 , H01L27/11
CPC分类号： H01L29/6675 , H01L27/0922 , H01L27/1104 , H01L29/78642
摘要： A polycrystalline silicon film (65) which is to be a channel is in trench (53) provided in a main surface (52) of a silicon substrate (51). A gate insulating film (63) is on the periphery of a polycrystalline silicon film (65). A gate electrode (61) is on the periphery of gate insulating film (63). A silicon oxide film (59) is on the periphery of gate electrode (61). A source/drain film (57) is on the periphery of silicon oxide film (59). A silicon oxide film (53) is on the periphery of source/drain film (57). A source/drain film (67) is electrically connected to polycrystalline silicon film (65). Source/drain film (57) is electrically connected to polycrystalline silicon film (65). Since polycrystalline silicon film (65) extends along the depth direction of trench (53), a channel length can be sufficient to prevent a short channel effect. Also, compared to the case in which an epitaxial layer is used as a channel, since polycrystalline silicon film (65) is used as a channel, a time required for manufacturing the device can be shortened.
摘要翻译：作为沟道的多晶硅膜（65）位于设置在硅基板（51）的主表面（52）中的沟槽（53）中。栅绝缘膜（63）位于多晶硅膜（65）的外围。栅电极（61）位于栅极绝缘膜（63）的周围。氧化硅膜（59）位于栅电极（61）的外围。源/漏膜（57）位于氧化硅膜（59）的外围。氧化硅膜（53）位于源极/漏极膜（57）的外围。源极/漏极膜（67）电连接到多晶硅膜（65）。源极/漏极膜（57）与多晶硅膜（65）电连接。由于多晶硅膜（65）沿着沟槽（53）的深度方向延伸，沟道长度可以足以防止短沟道效应。而且，与使用外延层作为沟道的情况相比，由于使用多晶硅膜（65）作为沟道，因此可以缩短制造器件所需的时间。

52. 发明公开

EP0552445A2 Field effect transistor 失效
标题翻译： Feldeffekttransistor和Verfahren zu seiner Herstellung。
公开(公告)号：EP0552445A2
公开(公告)日：1993-07-28
申请号：EP92120593.6
申请日：1992-12-02
申请人： MITSUBISHI DENKI KABUSHIKI KAISHA
发明人： Tsutsumi, Kazuhito, c/o Mitsubishi Denki K.K. LSI
IPC分类号： H01L29/772 , H01L27/11
CPC分类号： H01L29/6675 , H01L27/0922 , H01L27/1104 , H01L29/78642
摘要： A polycrystalline silicon film (65) which is to be a channel is in trench (53) provided in a main surface (52) of a silicon substrate (51). A gate insulating film (63) is on the periphery of a polycrystalline silicon film (65). A gate electrode (61) is on the periphery of gate insulating film (63). A silicon oxide film (59) is on the periphery of gate electrode (61). A source/drain film (57) is on the periphery of silicon oxide film (59). A silicon oxide film (53) is on the periphery of source/drain film (57). A source/drain film (67) is electrically connected to polycrystalline silicon film (65). Source/drain film (57) is electrically connected to polycrystalline silicon film (65). Since polycrystalline silicon film (65) extends along the depth direction of trench (53), a channel length can be sufficient to prevent a short channel effect. Also, compared to the case in which an epitaxial layer is used as a channel, since polycrystalline silicon film (65) is used as a channel, a time required for manufacturing the device can be shortened.
摘要翻译：作为沟道的多晶硅膜（65）位于设置在硅衬底（51）的主表面（52）中的沟槽（53）中。栅绝缘膜（63）位于多晶硅膜（65）的周围。栅电极（61）位于栅绝缘膜（63）的周围。氧化硅膜（59）位于栅极（61）的周围。源极/漏极膜（57）在氧化硅膜（59）的周围。氧化硅膜（53）位于源极/漏膜（57）的周围。源/漏膜（67）电连接到多晶硅膜（65）。源/漏膜（57）电连接到多晶硅膜（65）。由于多晶硅膜（65）沿着沟槽（53）的深度方向延伸，沟道长度可足以防止短沟道效应。此外，与使用外延层作为沟道的情况相比，由于使用多晶硅膜（65）作为沟道，因此可以缩短制造器件所需的时间。

53. 发明公开

EP0403449A3 Mixed technology intergrated device comprising complementary LDMOS power transistors, CMOS and vertical PNP integrated structures having an enhanced ability to withstand a relatively high supply voltage 失效
标题翻译：混合技术集成器件，包含补充LDMOS功率晶体管，CMOS和垂直PNP集成结构，具有增强的耐受能力，可以提供相对高的电源电压
公开(公告)号：EP0403449A3
公开(公告)日：1992-07-08
申请号：EP90830268.0
申请日：1990-06-14
申请人： SGS-THOMSON MICROELECTRONICS S.r.l.
发明人： Contiero, Claudio , Galbiati, Paola , Zullino, Lucia
IPC分类号： H01L27/06 , H01L21/82 , H01L27/092
CPC分类号： H01L27/0922 , H01L27/0623
摘要： Complementary LDMOS and MOS structures and vertical PNP transistors capable of withstanding a relatively high voltage may be realized in a mixed-technology integrated circuit of the so-called "smart power" type, by forming a phosphorus doped n-region of a similar diffusion profile, respectively in: the drain zone of the n-channel LDMOS transistors, in the body zone of the p-channel LDMOS transistors forming first CMOS structures; in the drain zone of n-channel MOS transistors belonging to second CMOS structures and in a base region near the emitter region of isolated collector, vertical PNP transistors, thus simultaneously achieving the result of increasing the voltage withstanding ability of all these monolithically integrated structures. The complementary LDMOS structures may be used either as power structures having a reduced conduction resistance or may be used for realizing CMOS stages capable of operating at a relatively high voltage (of about 20V) thus permitting a direct interfacing with VDMOS power devices without requiring any "level shifting" stages. The whole integrated circuit has less interfacing problems and improved electrical and reliability characteristics.

54. 发明公开

EP0414226A2 MOS field-effect transistor with sidewall spacers 失效
标题翻译： MOS-Feldeffekttransistor mit Seitenwand-Abstandsstücken。
公开(公告)号：EP0414226A2
公开(公告)日：1991-02-27
申请号：EP90116095.2
申请日：1990-08-22
申请人： NEC CORPORATION
发明人： Narita, Kaoru
IPC分类号： H01L29/772 , H01L27/092
CPC分类号： H01L29/7836 , H01L27/0922
摘要： In a n-channel MOS transistor of LDD structure with sidewall spacers, a p-type diffusion layer is formed to be on the surface of a n⁻ drain layer just underneath the sidewall spacer and to be separated from the channel region.
The low impurity concentration drain layer therefore becomes separated from the sidewall spacer, and thus degradation incident to LDD due to injection of hot carriers into the sidewall spacer can be prevented.
摘要翻译：在具有侧壁间隔物的LDD结构的n沟道MOS晶体管中，p型扩散层形成在刚好在侧壁间隔物下方的n +漏极层的表面上，并与沟道区分离。因此，低杂质浓度漏极层与侧壁间隔物分离，因此可以防止由于将热载流子注入侧壁间隔而入射到LDD的劣化。

55. 发明公开

EP0245515A4 SEMICONDUCTOR DEVICE 失效
标题翻译：半导体器件
公开(公告)号：EP0245515A4
公开(公告)日：1990-12-27
申请号：EP86906927
申请日：1986-11-12
申请人： HITACHI, LTD.
发明人： KITSUKAWA, GORO , ITOH, KIYOO , HORI, RYOICHI , WATANABE, TAKAO , SHIMOHIGASHI, KATSUHIRO , HOMMA, NORIYUKI
IPC分类号： H01L21/761 , H01L21/76 , H01L21/8238 , H01L21/8249 , H01L27/02 , H01L27/06 , H01L27/092 , H01L27/105 , H01L27/108 , H01L27/08 , H01L29/78
CPC分类号： H01L27/0214 , H01L27/0218 , H01L27/0623 , H01L27/0922 , H01L27/105 , H01L27/10805
摘要： To prevent the injection of minority carriers into a substrate when the potential undergoes changes due to noise or the like. In a semiconductor device having a substrate and sources and drains of insulated gate-type field-effect transistors or having collectors, bases and emitters of bipolar transistors in a plurality of isolation layers that are electrically isolated in the substrate, a voltage is applied to the substrate or to said plurality of isolation layers, said voltage falling outside a range in which the voltage applied to said sources and drains or to said collectors, bases and emitters can be varied.
摘要翻译：当电势由于噪声等而变化时，防止少数载流子注入基板。在具有绝缘栅极型场效应晶体管的基板和源极和漏极或在基板中电隔离的多个隔离层中具有双极晶体管的集电极，基极和发射极的半导体器件中，电压施加到衬底或所述多个隔离层，所述电压落在施加到所述源极和漏极或所述集电极，基极和发射极的电压可以变化的范围之外。

56. 发明公开

EP0386779A2 MOS field-effect transistor having a high breakdown voltage 失效
标题翻译： MOS-Feldeffekttransistor mit hoher Durchbruchsspannung。
公开(公告)号：EP0386779A2
公开(公告)日：1990-09-12
申请号：EP90104524.5
申请日：1990-03-09
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Shirai, Koji, c/o Intellectual Property Div. , Kawamura, Ken, c/o Intellectual Property Div.
IPC分类号： H01L29/78 , H01L27/088
CPC分类号： H01L29/7816 , H01L27/0922 , H01L29/0696 , H01L29/0847 , H01L29/41758 , H01L29/7809 , H01L29/7835
摘要： A semiconductor device comprises a semiconductor substrate (1) of a first conductivity type, a first well (2) of a second conductivity type formed on the semiconductor substrate (1) of the first conductivity type, a first impurity diffusion layer (5) of the first conductivity type formed on the well (2) without contacting the semiconductor substrate (1), a second impurity diffusion layer (6) of the second conductivity type which surrounds the first impurity diffusion layer (5) and has an impurity concentration which is higher than that of the well (2), a third impurity diffusion layer (7) of the first conductivity type formed within the second impurity diffusion layer (6) so as to contact neither the semiconductor substrate (1) nor the first impurity diffusion layer (5), a source electrode (10) connected to both the second impurity diffusion layer (6) and the third impurity diffusion layer (7), a gate electrode (12) which is formed between the first impurity diffusion layer (5) and the third impurity diffusion layer (7) and formed on the second impurity diffusion layer (6) so as to interpose an insulation film (11) therebetween, a drain electrode (9) connected to the first impurity diffusion layer (5), and a wiring layer extracted from the drain electrode (9) outside the semiconductor substrate (1).
摘要翻译：半导体器件包括第一导电类型的半导体衬底（1），形成在第一导电类型的半导体衬底（1）上的第二导电类型的第一阱（2），第一导电类型的第一杂质扩散层（5）在不与半导体衬底（1）接触的情况下在阱（2）上形成的第一导电类型，围绕第一杂质扩散层（5）的第二导电类型的第二杂质扩散层（6），其杂质浓度为高于阱（2）的第一杂质扩散层（7），形成在第二杂质扩散层（6）内的第一导电类型的第三杂质扩散层（7），以便与半导体衬底（1）和第一杂质扩散层（5），连接到第二杂质扩散层（6）和第三杂质扩散层（7）两者的源电极（10），形成在第一杂质扩散层（5）和第该第三杂质扩散层（7），形成在第二杂质扩散层（6）上，以便在其间插入绝缘膜（11），连接到第一杂质扩散层（5）的漏电极（9）层从半导体衬底（1）外部的漏电极（9）提取。

57. 发明授权

EP0175984B1 Semiconductor device comprising MOS transistors 有权
标题翻译：包含MOS晶体管的半导体器件
公开(公告)号：EP0175984B1
公开(公告)日：1990-03-14
申请号：EP85111272.2
申请日：1985-09-06
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Masuoka, Fujio c/o Patent Division , Ochii, Kiyofumi c/o Patent Division
IPC分类号： H01L27/06 , H01L23/52
CPC分类号： H01L27/0688 , H01L27/0922 , Y10S257/903

58. 发明公开

EP0319047A2 Power integrated circuit 失效
标题翻译： Integrierte Leistungsschaltung。
公开(公告)号：EP0319047A2
公开(公告)日：1989-06-07
申请号：EP88120266.7
申请日：1988-12-05
申请人： NISSAN MOTOR CO., LTD.
发明人： Mihara, Teruyoshi , Matsushita, Tsutomu
IPC分类号： H01L27/08 , H01L27/06 , H01L21/82
CPC分类号： H01L27/088 , H01L21/76 , H01L21/823462 , H01L27/0251 , H01L27/0922 , H03K17/063 , H03K17/0822
摘要： A single-chip integrated semiconductor device, in which a P-type isolation layer, to which the ground voltage is applied, is grown on a semiconductor substrate and a power voltage is applied to the substrate, in which a vettical MOSFET has a drain region of a first N-type well region formed in the P-type isolation layer so as to reach the semiconductor substrate therethrough, and is used in an output device for a load, in which a P-channel MOSFET is provided in the N-type well region formed in the P-type isolation layer, a constant voltage lower than the power voltage being applied to the N-type well region, and an N-channel MOSFET is formed in the P-type isolation layer, and in which the P-channel and N-channel MOSFETs constitute a CMOS circuit constructing a peripheral circuit for the vertical MOSFET.
摘要翻译：其中在半导体衬底上生长施加有接地电压的P型隔离层的单芯片集成半导体器件，并且向基板施加电源电压，其中VetFET具有漏极区域形成在P型隔离层中的第一N型阱区，以便到达半导体衬底，并且用于负载的输出装置，其中P型沟道MOSFET设置在N型形成在P型隔离层中的阱区，具有比施加到N型阱区的电压低的恒定电压，在P型隔离层中形成N沟道MOSFET，其中P型隔离层沟道和N沟道MOSFET构成构成垂直MOSFET的外围电路的CMOS电路。

59. 发明公开

EP0261666A1 Complementary type insulated gate field effect transistor 失效
标题翻译： KemplementärerFeldeffekt-Transistor mit isoliertem Gate。
公开(公告)号：EP0261666A1
公开(公告)日：1988-03-30
申请号：EP87113917.6
申请日：1987-09-23
申请人： NEC CORPORATION
发明人： Kasai, Naoki
IPC分类号： H01L27/08 , H01L29/04 , H01L21/82
CPC分类号： H01L27/0922 , H01L21/2815 , H01L21/8238 , H01L29/045 , H01L29/66787 , H01L29/7827
摘要： A new complementary type insulated gate field effect transistor is disclosed. A first side wall having (110) plane is perpendicularly formed from a major surface of a silicon substrate into the substrate and a P-channel type FET is provided on the first side wall. A second side wall having (100) plane is perpendicularly formed from the major surface into the substrate and an N-channel type FET is provided on the second side wall.
摘要翻译：公开了一种新的互补型绝缘栅场效应晶体管。具有（110）面的第一侧壁从硅衬底的主表面垂直地形成到衬底中，并且在第一侧壁上设置P沟道型FET。具有（100）面的第二侧壁从主表面垂直地形成到衬底中，并且在第二侧壁上设置有N沟道型FET。

60. 发明公开

EP0152625A3 Semiconductor device having a polycrystalline silicon-active region, method of producing it and an IC chip comprising such a semiconductor device 失效
标题翻译：具有多晶硅活性区域的半导体器件，其制造方法和包含这种半导体器件的IC芯片
公开(公告)号：EP0152625A3
公开(公告)日：1987-07-01
申请号：EP84116302
申请日：1984-12-24
申请人： SONY CORPORATION
发明人： Hayashi, Hisao
IPC分类号： H01L29/04 , H01L29/78 , H01L21/84
CPC分类号： H01L21/8238 , H01L27/0688 , H01L27/0922 , H01L27/1203 , H01L29/04 , H01L29/78675
摘要： A polycrystalline silicon layer is used to allow simultaneous fabrication of both N- and P-type MOSFET's on a common channel layer during integrated circuit fabrication. The polysilicon layer is between 20A and 750A thick, and preferably between 200A and 500A thick. These dimensions afford the polysilicon layer the high effective mobility, low threshold voltage and low leakage current characteristics, especially if the vapor-deposited polysilicon layer is annealed and/or ion implanted with Si + or Ge + after deposition. Application of the polysilicon layer over adjoining insulating and P-type semiconducting areas allows the single polysilicon layer to serve as active terminals and channels of both conductivity types of MOS transistors without intervening insulating or semiconducting layers. Deposition of the polysilicon layer in direct contact with a single-crystal substrate enhances the beneficial electrical properties of the polysilicon layer, especially if the polysilicon layer is annealed following deposition.

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