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51. 发明公开

EP1532633A1 DUAL LOOP SENSING SCHEME FOR RESISTIVE MEMORY ELEMENTS 有权
标题翻译：双研磨阅读计划FOR电阻存储器单元
公开(公告)号：EP1532633A1
公开(公告)日：2005-05-25
申请号：EP03788292.5
申请日：2003-07-30
申请人： MICRON TECHNOLOGY, INC.
发明人： BAKER, R., Jacob
IPC分类号： G11C11/16 , G11C7/06
CPC分类号： G11C13/004 , G11C7/06 , G11C11/1673 , G11C11/1693 , G11C13/0061 , G11C2013/0057

52. 发明公开

EP1420410A2 Power-saving reading of magnetic memory devices 审中-公开
标题翻译：磁存储设备的节能读取
公开(公告)号：EP1420410A2
公开(公告)日：2004-05-19
申请号：EP03012090.1
申请日：2003-05-28
申请人： Hewlett-Packard Development Company, L.P.
发明人： Smith, Kenneth Kay , Perner, Frederick A.
IPC分类号： G11C11/16
CPC分类号： G11C7/062 , G11C11/1673 , G11C13/0061 , G11C27/022 , G11C2013/0057
摘要： The present disclosure relates to power-saving reading of magnetic memory devices. In one arrangement, a method comprises pulsing a voltage on the array, and obtaining a voltage value indicative of a memory state of the target memory cell from the voltage pulse using a sensing circuit that is electrically connected to the target memory cell. In another arrangement, a method comprises pulsing an array voltage on a plurality of row and column conductors of the array, connecting a sensing circuit to a conductor that is electrically coupled to the target memory cell, the sensing circuit including a sense element, and determining the voltage drop across the sense element of the sensing circuit during the voltage pulse, the voltage drop being indicative of a memory state of the target memory cell.
摘要翻译：本公开涉及磁存储器设备的节能读取。在一种布置中，一种方法包括使用电连接到目标存储器单元的感测电路对阵列上的电压施加脉冲，并且从电压脉冲获得指示目标存储器单元的存储器状态的电压值。在另一种布置中，一种方法包括在阵列的多个行和列导体上脉冲阵列电压，将感测电路连接到电耦合到目标存储器单元的导体，感测电路包括感测元件，以及确定在电压脉冲期间感测电路的感测元件两端的电压降，所述电压降表示目标存储器单元的存储器状态。

53. 发明授权

EP3985671B1 MEMORY DEVICE INCLUDING PHASE CHANGE MEMORY CELL AND OPERATION METHOD THEREOF 有权
公开(公告)号：EP3985671B1
公开(公告)日：2024-10-09
申请号：EP21202523.3
申请日：2021-10-13
IPC分类号： G11C13/00
CPC分类号： G11C13/0004 , G11C13/0026 , G11C13/0028 , G11C13/0038 , G11C13/0069 , G11C13/0097 , G11C2013/009220130101 , G11C13/003 , G11C2213/7620130101 , G11C2013/007820130101 , G11C2213/1520130101 , G11C13/0061

54. 发明授权

EP3607551B1 MEMORY DEVICES FORMED FROM CORRELATED ELECTRON MATERIALS 有权
公开(公告)号：EP3607551B1
公开(公告)日：2024-09-18
申请号：EP18717670.6
申请日：2018-04-04
IPC分类号： G11C13/00
CPC分类号： G11C13/0002 , G11C13/003 , G11C2013/007120130101 , G11C2213/7920130101 , G11C2213/8220130101 , G11C13/0061 , G11C13/0069 , G11C13/0007

55. 发明公开

EP3117435A4 MITIGATING READ DISTURB IN A CROSS-POINT MEMORY 有权
公开(公告)号：EP3117435A4
公开(公告)日：2017-11-01
申请号：EP15761871
申请日：2015-03-09
申请人： INTEL CORP
发明人： CHU DANIEL J , PANGAL KIRAN , FRANKLIN NATHAN R , DAMLE PRASHANT S , CHAOHONG HU
IPC分类号： G11C13/00 , G11C7/06 , G11C7/10
CPC分类号： G11C13/004 , G11C11/5678 , G11C13/0004 , G11C13/0033 , G11C13/0035 , G11C13/0061 , G11C2013/0047 , G11C2013/0052

56. 发明公开

EP3201925A1 APPARATUS AND METHODS FOR SENSING HARD BIT AND SOFT BITS 有权
标题翻译：用于检测硬位和软位的装置和方法
公开(公告)号：EP3201925A1
公开(公告)日：2017-08-09
申请号：EP15760047.9
申请日：2015-08-30
申请人： SanDisk Technologies LLC
发明人： SIAU, Chang , LEE, Jeffrey Koon Yee , YAN, Tianhong , CHEN, Yingchang , BALAKRISHNAN, Gopinath , LIU, Tz-Yi
IPC分类号： G11C11/16 , G11C13/00 , G11C16/28 , G11C16/32
CPC分类号： G11C13/004 , G11C13/0028 , G11C13/0061 , G11C16/28 , G11C16/32 , G11C27/02 , G11C2013/0054
摘要： A method is provided for reading a memory cell of a nonvolatile memory system. The method includes generating a hard bit and N soft bits for the memory cell in a total time corresponding to a single read latency period and N+1 data transfer times.
摘要翻译：提供了一种用于读取非易失性存储器系统的存储器单元的方法。该方法包括在对应于单个读取等待时间段和N + 1个数据传输时间的总时间内为存储器单元生成硬位和N个软位。

57. 发明公开

EP3117436A1 SELECTOR DEVICE FOR TWO-TERMINAL MEMORY 有权
标题翻译： SELEKTORVORRICHTUNGFÜRSPEICHER MIT ZWEIENDGERÄTEN
公开(公告)号：EP3117436A1
公开(公告)日：2017-01-18
申请号：EP15762196.2
申请日：2015-02-24
申请人： Crossbar, Inc.
发明人： JO, Sung Hyun
IPC分类号： G11C13/00
CPC分类号： G11C13/0097 , G11C11/16 , G11C11/1659 , G11C11/56 , G11C13/0002 , G11C13/0007 , G11C13/0011 , G11C13/003 , G11C13/004 , G11C13/0061 , G11C13/0069 , G11C2213/15 , G11C2213/55 , G11C2213/71 , G11C2213/76 , G11C2213/77 , H01L27/2409 , H01L27/2418 , H01L27/2481 , H01L27/249 , H01L45/08 , H01L45/085 , H01L45/1233 , H01L45/1266 , H01L45/145 , H01L45/146 , H01L45/16 , H01L45/1608
摘要： Solid-state memory having a non-linear current-voltage (I-V) response is provided. By way of example, the solid-state memory can be a selector device. The selector device can be formed in series with a non-volatile memory device via a monolithic fabrication process. Further, the selector device can provide a substantially non-linear I-V response suitable to mitigate leakage current for the non-volatile memory device. In various disclosed embodiments, the series combination of the selector device and the non-volatile memory device can serve as one of a set of memory cells in a 1-transistor, many-resistor resistive memory cell array.
摘要翻译：提供具有非线性电流 - 电压（I-V）响应的固态存储器。作为示例，固态存储器可以是选择器装置。选择器装置可以通过单片制造工艺与非易失性存储器件串联形成。此外，选择器装置可以提供适于缓解非易失性存储器件的泄漏电流的基本上非线性的I-V响应。在各种公开的实施例中，选择器装置和非易失性存储装置的串联组合可以用作1-晶体管，多电阻电阻存储单元阵列中的一组存储单元。

58. 发明公开

EP2867897A4 MULTI-LEVEL CELL MEMORY 有权转让
标题翻译：多级单元存储器
公开(公告)号：EP2867897A4
公开(公告)日：2016-02-17
申请号：EP12880177
申请日：2012-06-28
申请人： HEWLETT PACKARD DEVELOPMENT CO
发明人： MURALIMANOHAR NAVEEN , YOON HAN BIN , JOUPPI NORMAN PAUL
IPC分类号： G11C7/10 , G11C11/56 , G11C13/00 , G11C16/06 , G11C16/26
CPC分类号： G11C11/5678 , G11C7/1057 , G11C11/56 , G11C11/5628 , G11C11/5642 , G11C13/0004 , G11C13/004 , G11C13/0061 , G11C13/0069 , G11C16/06 , G11C16/26 , G11C2211/5642
摘要： A multi-level cell memory includes a memory cell that stores two or more bits of information; a sensing circuit coupled to the memory cell; and a row buffer structure comprising a split page buffer having a first page buffer and a second page buffer. The sensing circuit operates to read from the memory cell, places a first bit in one of the first page buffer and the second page buffer, and places the second bit in one of the first page buffer and the second page buffer.

59. 发明授权

EP2089887B1 READ ENHANCEMENT FOR MEMORY 有权
标题翻译：阅读扩展内存
公开(公告)号：EP2089887B1
公开(公告)日：2015-12-23
申请号：EP07826901.6
申请日：2007-10-29
申请人： NXP B.V.
发明人： MAYOR, Cedric
IPC分类号： G11C13/00 , G11C16/28 , G11C7/06
CPC分类号： G11C13/004 , G11C7/065 , G11C13/0061 , G11C2013/0054

60. 发明公开

EP2951834A1 NON-VOLATILE MULTI-LEVEL-CELL MEMORY WITH DECOUPLED BITS FOR HIGHER PERFORMANCE AND ENERGY EFFICIENCY 审中-公开
标题翻译：具有经去耦BITS不挥发的多级存储器单元获得更高的性能和能效
公开(公告)号：EP2951834A1
公开(公告)日：2015-12-09
申请号：EP13874163.2
申请日：2013-01-31
申请人： Hewlett-Packard Development Company, L.P.
发明人： MURALIMANOHAR, Naveen , YOON, Han Bin , JOUPPI, Norman, Paul
IPC分类号： G11C16/06 , G11C16/26
CPC分类号： G11C13/0061 , G06F12/0246 , G11C11/5628 , G11C11/5678 , G11C11/5685 , G11C13/0002 , G11C13/0004 , G11C13/004 , G11C13/0069 , G11C16/10 , G11C16/26 , G11C2207/2272 , Y02D10/13
摘要： A non-volatile multi-level cell (“MLC”) memory device is disclosed. The memory device has an array of non-volatile memory cells, an array of non-volatile memory cells, with each non-volatile memory cell storing multiple groups of bits. A row buffer in the memory device has multiple buffer portions, each buffer portion storing one or more bits from the memory cells and having different read and write latencies and energies.

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