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41. 发明公开

EP1903611A3 Semiconductor device and manufacturing method thereof 审中-公开
公开(公告)号：EP1903611A3
公开(公告)日：2009-04-29
申请号：EP07116351.3
申请日：2007-09-13
申请人： Panasonic Corporation
发明人： Kudo, Chiaki Matsushita Electric Ind. Co., Ltd. , Ogawa, Hisashi Matsushita Electric Industrial Co., Ltd.
IPC分类号： H01L29/423 , H01L21/28 , H01L21/8238 , H01L21/768
CPC分类号： H01L29/42376 , H01L21/28123 , H01L21/823456 , H01L21/82385 , H01L27/0207 , H01L29/4238
摘要： A semiconductor device includes: an isolation region formed in a semiconductor substrate; an active region surrounded by the isolation region; and a first gate electrode formed on the isolation region and the active region and including a first region on the isolation region. The first region has a pattern width in a gate length direction larger than a pattern width of the first gate electrode on the active region. The first region includes a part having a film thickness different from a film thickness of the first gate electrode on the active region.

42. 发明公开

EP1801856A1 Method for gate electrode height control 审中-公开
标题翻译：一种用于控制栅电极的高度方法
公开(公告)号：EP1801856A1
公开(公告)日：2007-06-27
申请号：EP05447291.5
申请日：2005-12-23
申请人： INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM ( IMEC)
发明人： Veloso, Anabela
IPC分类号： H01L21/28 , H01L21/336
CPC分类号： H01L29/4975 , H01L21/28052 , H01L21/28097 , H01L21/823443 , H01L21/823456 , H01L21/823835 , H01L21/82385 , H01L29/66507 , H01L29/66545
摘要： The present invention relates to a method for controlling the gate electrode in a silicidation process, comprising the steps of :
- applying a sacrificial cap layer on top of each of at least one gate electrode, each of the at least one gate electrode deposited with a given height on a semiconductor substrate,
- covering said semiconductor substrate provided with said at least one gate electrode having a sacrificial cap layer on top, with a material,
- performing a CMP planarisation step,
- removing at least the material until on top of each of the at least one gate electrode the sacrificial cap layer is exposed,
- removing the sacrificial cap layer from each of the at least one gate electrode, yielding each of the at least one gate electrode still having the given height.

43. 发明授权

EP0832498B1 METHOD OF MANUFACTURING A POWER INTEGRATED CIRCUIT DEVICE 失效
标题翻译：过程中的集成电源电路
公开(公告)号：EP0832498B1
公开(公告)日：2006-11-22
申请号：EP97901235.8
申请日：1997-02-13
申请人： Koninklijke Philips Electronics N.V.
发明人： LUDIKHUIZE, Adrianus Willem , VAN DORT, Maarten
IPC分类号： H01L21/8232 , H01L27/088 , H01L21/336
CPC分类号： H01L29/0852 , H01L21/26586 , H01L21/823412 , H01L21/823456 , H01L21/823462 , H01L27/0922 , H01L29/0847 , H01L29/1095 , H01L29/42368 , H01L29/66681 , H01L29/7816
摘要： A deep diffusion of the back-gate region provided in a self-aligned manner with respect to the gate electrode is necessary in a DMOS transistor for obtaining a sufficiently high punch-through voltage between source and drain. The combination of a comparatively heavy back-gate implantation and a light source implantation and a heavy source implantation with spacer on the gate electrode, and the use of interstitial diffusion and accelerated diffusion owing to crystal damage render it possible to carry out said diffusion of the back-gate region at a comparatively low temperature, for example below 950 DEG C. This renders it possible to integrate a DMOST into, for example, standard VLSI CMOS where first delta Vth and channel-profile implantations are carried out, and subsequently the poly gates are provided, which means that a diffusion step at a temperature above 1,000 DEG C. of long duration is no longer allowed. The effect may be enhanced in that the doping of the back-gate region is increased during the p-type LDD implantation of a p-channel MOS and/or the p-type well implantation of an n-channel MOS.

44. 发明公开

EP1225626A3 Semiconductor integrated circuit device and manufacture method therefor 有权
标题翻译：一种半导体集成电路，及其制造方法
公开(公告)号：EP1225626A3
公开(公告)日：2005-01-12
申请号：EP02250304.9
申请日：2002-01-16
申请人： FUJI ELECTRIC CO., LTD.
发明人： Kitamura, Akio
IPC分类号： H01L21/8234
CPC分类号： H01L21/8249 , H01L21/761 , H01L21/823412 , H01L21/823456 , H01L21/823493 , H01L27/0635
摘要： The object of the present invention is to mount a submicron CMOS transistor on the same substrate together with an analog CMOS transistor, a high voltage-resistance MOS transistor, a bipolar transistor, a diode, or a diffusion resistor, without degrading the characteristics of these components. When a punch-through stopper area is formed on a main surface side of a semiconductor substrate 1, an area in which an analog CMOS transistor, a high voltage-resistance MOS transistor, a bipolar transistor, a diode, or a diffusion resistor is formed is masked, and for example, an ion injection is then carried out. Thus, a punch-through stopper area 4 is formed in the area in which a submicron CMOS transistor is formed, while preventing the formation of a punch-through stopper area in the area in which an analog CMOS transistor, a high voltage-resistance MOS transistor, a bipolar transistor, a diode, or a diffusion resistor is formed.

45. 发明公开

EP1487023A2 Semiconductor device comprising a MIS transistor and method for manufacturing the same 审中-公开
标题翻译： Halbleiteranordnung mit einem MIS-Transistor und Verfahren zu deren Herstellung
公开(公告)号：EP1487023A2
公开(公告)日：2004-12-15
申请号：EP04013680.6
申请日：2004-06-09
申请人： Denso Corporation
发明人： Shiraki, Satoshi c/o DENSO CORPORATION , Nakayama, Yoshiaki c/o DENSO CORPORATION , Mizuno, Shoji c/o DENSO CORPORATION , Nakano, Takashi c/o DENSO CORPORATION , Yamada, Akira c/o DENSO CORPORATION
IPC分类号： H01L29/78 , H01L29/423 , H01L29/10 , H01L21/336
CPC分类号： H01L29/7824 , H01L21/26586 , H01L21/76286 , H01L21/763 , H01L21/823418 , H01L21/823456 , H01L21/823462 , H01L21/823481 , H01L29/0696 , H01L29/1041 , H01L29/105 , H01L29/1095 , H01L29/4236 , H01L29/42368 , H01L29/42376 , H01L29/4238 , H01L29/66681 , H01L29/66795 , H01L29/7825 , H01L29/7831 , H01L29/7835
摘要： A semiconductor device includes: a semiconductor substrate (3) with a principal plane (3a); a base region (20, 21) disposed on the principal plane (3a); a source region (22) disposed on the principal plane (3a) in the base region (20, 21) to be shallower than the base region (20, 21); a drain region (25) disposed on the principal plane (3a), and spaced to the base region (20, 21); a trench (26) disposed on the principal plane (3a); a trench gate electrode (28) disposed in the trench (26) through a trench gate insulation film (27); a planer gate electrode (31) disposed on the principal plane (3a) of the semiconductor substrate (3) through a planer gate insulation film (30); and an impurity diffusion region (35) having high concentration of impurities and disposed in a portion of the base region (20, 21) to be a channel region facing the planer gate electrode (31).
摘要翻译：诸如横向功率MOS晶体管的半导体器件包括：具有主平面（3a）的半导体衬底（3）; 设置在主平面（3a）上的基部区域（20,21）; 设置在所述基极区域（20,21）中的所述主平面（3a）上以比所述基极区域（20,21）更浅的源极区域（22）。设置在所述主平面（3a）上并与所述基底区域间隔开的漏极区域（25）; 设置在主平面（3a）上的沟槽（26）; 通过沟槽栅极绝缘膜（27）设置在所述沟槽（26）中的沟槽栅电极（28）; 通过平面栅极绝缘膜（30）设置在半导体衬底（3）的主平面（3a）上的平面栅电极（31）; 以及杂质扩散区域（35），其具有高浓度的杂质，并且设置在所述基极区域（20,21）的一部分中，以形成面对所述平面栅电极（31）的沟道区域。

46. 发明授权

EP0859401B1 Halbleiterkörper mit selbstjustierender Struktur 失效
标题翻译：具有自对准结构的半导体本体
公开(公告)号：EP0859401B1
公开(公告)日：2004-12-01
申请号：EP98100724.8
申请日：1998-01-16
申请人： Infineon Technologies AG
发明人： Stecher, Mattihas, Dr. , Peri, Hermann
IPC分类号： H01L21/033 , H01L21/336 , H01L21/8249 , H01L27/06 , H01L29/78
CPC分类号： H01L21/76897 , H01L21/823456 , H01L29/7809

47. 发明公开

EP1449217A1 A METHOD FOR MAKING SELF-REGISTERING NON-LITHOGRAPHIC TRANSISTORS WITH ULTRASHORT CHANNEL LENGTHS 审中-公开
标题翻译：用于生产自组织与超短沟道长度nonlithographic TRANSISTORS
公开(公告)号：EP1449217A1
公开(公告)日：2004-08-25
申请号：EP02803936.0
申请日：2002-11-01
申请人： Thin Film Electronics ASA
发明人： GUDESEN, Hans, Gude
IPC分类号： G11C11/00 , H01L21/8239
CPC分类号： H01L21/823456 , H01L21/823418
摘要： In a method for making transistors with ultrashort channel length, the deposition of respectively source, drain and gate electrodes initially can be performed with prior art technology limiting the electrode dimensions according to applicable design rules, while the dimensions of every second of these electrodes in subsequent process steps can be adjusted as desired. A channel area is formed between a source and a drain electrode without being constrained by any design rule and this allows the formation of transistor channels with extremely short channel lengths L, e.g. well below 10 nm. Correspondingly the width of the gate electrodes can be adjusted to also obtain a large channel width W and hence provide transistors with almost arbitrarily large aspect ratios W/L and thus desirable switching and current characteristics. The method can be applied to make any kind of field-effect transistor, even on the same substrate and may be adjusted for the fabrication of other kinds of transistor structures as well.

48. 发明公开

EP1334517A2 GATE PROCESS FOR DRAM ARRAY AND LOGIC DEVICES ON SAME CHIP 有权
标题翻译： GATE制造工艺的DRAM面积和逻辑组件的同一芯片上
公开(公告)号：EP1334517A2
公开(公告)日：2003-08-13
申请号：EP01988493.1
申请日：2001-11-13
申请人： Infineon Technologies North America Corp. , International Business MachinesCorporation
发明人： DIVAKARUNI, Ramachandra , WEYBRIGHT, Mary, E. , HORN, Peter , BRONNER, Gary , CONTI, Richard, A. , SCHROEDER, Uwe , GAMBINO, Jeffrey, Peter
IPC分类号： H01L21/8242
CPC分类号： H01L27/10894 , H01L21/76897 , H01L21/823456 , H01L27/1052 , H01L27/10873
摘要： Two different gate conductor dielectric caps are used in the array and support device regions so that the bitline contact can be fabricated in the array region, but a thinner hard mask can be used for better linewidth control in the support device region. The thinner dielectric cap is made into dielectric spacers in the array device regions during support mask etching. These dielectric spacers allow for the array gate conductor resist line to be made smaller than the final gate conductor linewidth. This widens the array gate conductor processing window. The second dielectric cap layer improves linewidth control for the support devices and the array devices. Two separate gate conductor lithography steps and gate conductor dielectric etches are carried out in the present invention to optimize the gate conductor linewidth control in the array and support device regions. The gate conductors in the array and support devices regions are etched simultaneously to reduce production cost. In additional embodiments of the invention, dual workfunction support device transistors with or without salicide can be fabricated with an array including borderless contacts.

49. 发明公开

EP0746033A2 Improvements in or relating to semiconductor processing 失效
标题翻译：改进或与半导体制造有关
公开(公告)号：EP0746033A2
公开(公告)日：1996-12-04
申请号：EP96108739.2
申请日：1996-05-31
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Torreno, Manuel L. , Smayling, Michael C. , Parker, Ronald N.
IPC分类号： H01L27/06 , H01L27/105 , H01L27/088
CPC分类号： H01L21/823456 , H01L27/0623 , H01L27/088
摘要： A process flow which can be used to fabricate a high frequency bipolar transistor 147, a power transistor 146, and non-power MOS devices on a single substrate while maintaining superior performance. The process flow forms an initial high-voltage tank 170 in substrate 150. A thin epitaxial layer 156 is formed on the substrate which overlies the initial high voltage tank and Diffusion Under Film, DUF, region 154. The high voltage tank is extended through the epitaxial layer and power transistor 146 is formed in the high voltage tank and high frequency bipolar transistor 147 is formed in the epitaxial layer using the DUF region as a deep collector. Other types of low voltage devices 139 and 140 and mid voltage devices 141-145 and 148-149 are formed unaffected by the presence of epitaxial layer 156. A single chip transmitter 400 and a single chip receiver 410 is fabricated with high frequency transistors and power devices. A single chip disk controller 460 is fabricated with high frequency transistors and power devices.

50. 发明公开

EP0453070A2 Method of manufacturing an intelligent power semiconductor device 失效
标题翻译： Verfahren zur Herstellung eines smarten Leistungshalbleiterbauelements。
公开(公告)号：EP0453070A2
公开(公告)日：1991-10-23
申请号：EP91301443.7
申请日：1991-02-22
申请人： Nippon Motorola Ltd.
发明人： Ishiguro, Takeshi
IPC分类号： H01L27/088 , H01L21/82 , H01L27/06
CPC分类号： H01L27/088 , H01L21/761 , H01L21/823456
摘要： An improved method is disclosed for manufacturing an intelligent power semiconductor device, which comprises sequential steps of forming an element forming region on a semiconductor substrate, forming a gate insulation film for a power transistor, forming a conductive layer for a gate electrode of power transistor on the gate insulation film, forming a tab region for the power transistor, forming a gate insulation film for a small signal transistor, introducing impurities into channel region of the small signal transistor to adjust the threshold voltage thereof, forming a conductive layer for a gate electrode of the small signal transistor, and forming a source electrode and a drain electrode for each of the transistors. Since the process of forming the tab region of the power transistor is followed by the process of introducing impurities into the channel region of the small signal transistor, the threshold voltage of the small signal transistor is not influence by the process of forming the tab region of the power transistor.
摘要翻译：公开了一种用于制造智能功率半导体器件的改进方法，其包括在半导体衬底上形成元件形成区域的顺序步骤，形成用于功率晶体管的栅极绝缘膜，形成用于功率晶体管的栅电极的导电层栅极绝缘膜，形成用于功率晶体管的突片区域，形成用于小信号晶体管的栅极绝缘膜，将杂质引入小信号晶体管的沟道区域中以调整其阈值电压，形成用于栅电极的导电层的小信号晶体管，并且为每个晶体管形成源电极和漏电极。由于形成功率晶体管的突片区域的过程之后是将杂质引入小信号晶体管的沟道区域的过程，所以小信号晶体管的阈值电压不受形成功率晶体管。

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