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41. 发明授权

EP0229144B1 WAFER-SCALE INTEGRATED CIRCUIT MEMORY 失效
标题翻译：超大规模集成电路存储器
公开(公告)号：EP0229144B1
公开(公告)日：1992-01-15
申请号：EP86904285.3
申请日：1986-07-11
申请人： ANAMARTIC LIMITED
发明人： BRENT, Michael , MACDONALD, Neal
IPC分类号： G11C7/00 , G11C8/00 , G11C11/406 , G06F11/20
CPC分类号： G11C8/00 , G11C7/00 , G11C7/22 , G11C8/12 , G11C8/18 , G11C11/406 , G11C29/006
摘要： A wafer scale integrated circuit comprises a few hundred modules (10) which can be connected into a long chain by commands sent to the modules along a transmit path set up by way of module inputs (XINN, XINE, XINS, XINW) from neighbouring modules and outputs thereto (XOUTN, XOUTE, XOUTS, XOUTW), only one of which is enabled by one of four selection signals (SELN, SELE, SELS, SELW) acting both on transmit path logic (20) and on receive path logic (21) in a return path. Each module includes configuration logic (22) which decodes commands providing the selection signals (SELN, etc), a READ signal and a WRITE signal. The configuration logic (22) is addressed when a bit is presented thereto by the transmit path simultaneously with assertion of a signal (CMND) which is supplied globally to all modules. The address configuration logic clocks the bit along a shift register and the selected command is determined by the position of the bit at the time that the global signal (CMND) is terminated. Each module includes a memory unit (23) including a free running address counter. When the WRITE command appears a data stream on the transmit path is read into the memory. When READ appears, the contents of the memory are read out onto the return path. Memory refresh occurs conventionally under control of the free-running address counter. In order to avoid heavy current in any of the power distribution conductors on the wafer, the count cycles of the free-running address counters are staggered.

42. 发明公开

EP0315792A3 Interconnection system for integrated circuit chips 失效
标题翻译：集成电路板互连系统
公开(公告)号：EP0315792A3
公开(公告)日：1991-12-18
申请号：EP88117121.9
申请日：1988-10-14
申请人： LORAL AEROSPACE CORPORATION
发明人： Chall, Louis Edmond, Jr.
IPC分类号： H01L23/48 , H05K7/20 , H01L23/52
CPC分类号： H01L23/52 , G01R31/318505 , G11C29/006 , H01L23/13 , H01L23/473 , H01L23/5385 , H01L2924/0002 , H01L2924/15162 , H01L2924/3011 , H05K1/0286 , H05K1/142 , H05K3/3442 , H05K3/403 , H05K7/20545 , H05K2201/09181 , H05K2201/09418 , H05K2201/1053 , H05K2201/10727 , Y02P70/613 , H01L2924/00
摘要： A novel packaging system for VLSI circuits allows low-cost construction and maintenance of complex high density high-performance devices with low power requirements. The devices can be individually created by software means from a small selection of standardizable IC chips by disposing a plurality of chips in leadless chip carriers in a mosaic on a substrate, and configuring them by software to selectively communicate with other chips of the mosaic or even to individually change their operating function. The immediate juxtaposition of the chip carries in the mosaic eliminates transmission line data skew, and also allows considerable savings in chip space and power requirements by dispensing with interconnection drivers, receivers and bonding pads. The chip carrier mosaics may be assembled into modules suitable for plug-in connection to an interconnecting backplane to create even larger devices, and individual modules can be dynamically tested in their high-performance mode by configuring one or more modules as test modules and either plugging them into modules to be tested or making them a permanent part of the device's module array.

43. 发明授权

EP0212208B1 Schaltungsanordnung zum Prüfen integrierter Schaltungseinheiten 失效
标题翻译：用于测试集成电路单元的电路布置
公开(公告)号：EP0212208B1
公开(公告)日：1991-09-25
申请号：EP86109401.9
申请日：1986-07-09
申请人： Krug, Heinz
发明人： Krug, Heinz
IPC分类号： G01R31/28 , G06F11/26
CPC分类号： G01R31/3185 , G01R31/318516 , G11C29/006 , Y10S257/92
摘要： The circuit arrangement is for testing circuit units (2) which take the form of integrated circuits on a common mother board and can be operated on the mother board via common supply lines and input lines. In the circuit arrangement, a test circuit (3) and switching stages (10) take the form of integrated circuits on the same mother board. The switching stages (10) are switched on by the test circuit (3) via connecting lines (12, 13) for connecting the test circuit to the circuit units. The test circuit is equipped with an output circuit (7) for delivering the test results.

44. 发明授权

EP0190813B1 Processing cell for fault tolerant arrays 失效转让
标题翻译：处理容器的容错阵列
公开(公告)号：EP0190813B1
公开(公告)日：1991-09-18
申请号：EP86300018.8
申请日：1986-01-03
申请人： Secretary of State for Defence in Her Britannic Majesty's Gov. of the United Kingdom of Great Britain and Northern Ireland
发明人： Evans, Richard Anthony
IPC分类号： G06F11/00 , G06F11/20
CPC分类号： G11C29/006 , G06F11/267 , G06F15/8023

45. 发明授权

EP0261164B1 RANDOM ADDRESS SYSTEM FOR CIRCUIT MODULES 失效
标题翻译：电路模块随机寻址系统
公开(公告)号：EP0261164B1
公开(公告)日：1991-07-24
申请号：EP87901599.8
申请日：1987-03-18
申请人： ANAMARTIC LIMITED
发明人： SINCLAIR, Alan, Welsh
IPC分类号： G06F11/20
CPC分类号： G11C29/006
摘要： The wafer scale integrated circuit comprises an array of undiced chips or modules (10), each of which includes a data storing or processing circuit, e.g. a dynamic RAM, and configuration logic. Channels (11) for data and control signals exist between each module and its (N, S, E and W) neighbours and a target module in the array may be addressed by setting up a path (12) through the array from an entry module to the target module. The addressing is effected by sending a stream of link commands, each of which tells a module to link on to its (N, S, E or W) neighbour. Each module responds to the first command of the stream and then sends on the stream stripped of this first command. In an alternative embodiment the link commands are transmitted from module to module in parallel, each module responds to the command at the least significant end and strips it off by a shift of the commands in the least significant direction before the commands pass to the next module. A control circuit for addressing modules in the array at random forms a unique set of link commands for each module to be addressed, these command sets being such that the paths to the various modules form a densely branching tree commencing from the entry module.

46. 发明公开

EP0378613A1 WAFER SCALE INTEGRATED CIRCUITS 失效
标题翻译：半导体晶圆尺寸的集成电路。
公开(公告)号：EP0378613A1
公开(公告)日：1990-07-25
申请号：EP89906418.0
申请日：1989-05-31
申请人： ANAMARTIC LIMITED
发明人： BRENT, Michael , MACDONALD, Neal , MARSH, Anthony
IPC分类号： G11C5 , G11C29 , H01L23
CPC分类号： H01L23/52 , G11C5/063 , G11C29/006 , H01L23/5286 , H01L24/06 , H01L2224/05554 , H01L2224/48091 , H01L2224/4813 , H01L2924/14 , H01L2924/00014 , H01L2924/00
摘要： Des circuits intégrés similaires ou "puces" (10) sur une tranche (22) supportée sur une carte de circuits imprimés (24) sont alimentés en courant par des fils de connexion (20) VCC et VSS soudés en points de couture à des plots sur toutes les puces (10). Les fils de connexion sont interrompus au niveau de l'équateur de sorte qu'une anomalie au niveau de la ligne d'alimentation dans la moitié supérieure ou inférieure de la tranche n'affectera pas d'autres puces dans la moitié inférieure de la tranche, et vice-versa. Des circuits globaux d'acheminement des signaux (18) WCK (synchronisation tranche) et CMND (instruction) sont traités de la même manière et sont constitués de métal interrompu dans une bande équatoriale (26). Chaque puce (10) possède des plots de connexion d'entrée et de sortie pour l'entrée et la sortie de données vers une chaîne de puces dont la croissance est assurée au moyen de connexions inter-modules de manière connue en soi. On peut ainsi masquer les puces à l'aide de réticules similaires tout en ayant toujours des puces marginales (10') disponibles dont les plots d'entrée et de sortie peuvent servir à faire des connexions externes, via des fils de connexion (38).

47. 发明公开

EP0244443A4 COMMUNICATION NETWORK FOR MULTIPROCESSOR PACKET COMMUNICATION. 失效
标题翻译：输电网络的数据包传输的几个计算机之间。
公开(公告)号：EP0244443A4
公开(公告)日：1989-06-21
申请号：EP86906183
申请日：1986-09-26
申请人： SCHLUMBERGER TECHNOLOGY CORP
发明人： DAVIS ALAN LYNN , ROBISON SHANE V , STEVENS KENNETH SCOTT
IPC分类号： G06F15/16 , G06F11/00 , G06F11/14 , G06F15/173 , G06F15/80 , G11C29/00 , H04L12/701 , H04L12/703 , G06F13/14 , G06F13/28 , G06F13/38
CPC分类号： H04L45/00 , G06F11/0724 , G06F11/076 , G06F11/14 , G06F15/17381 , G11C29/006 , H04L45/28
摘要： A communication network (70) formed by a plurality of communication processors (74) which are connected together in such a way that messages can be sent efficiently between any two processors in a muliprocessor data processing system. Each data processor is coupled to a communication processor (74) which is responsible for sending and receiving messages from other communication processors which are coupled to other data processors. The communication processors are organized into a two dimensional hexagonal array. The communication processors route a message from a sending processor to a receiving processor through the communication network. The message routing algorithm used by each of communication processors automatically reroutes messages around communication bottlenecks created by a malfunctioning communication processor or by a local communication overload.

48. 发明公开

EP0219413A3 An array reconfiguration apparatus and method particularly adapted for use with very large scale integrated circuits 失效
标题翻译：适用于非常大规模集成电路的阵列重构装置和方法特别适用
公开(公告)号：EP0219413A3
公开(公告)日：1988-09-28
申请号：EP86402162
申请日：1986-10-02
申请人： ITT INDUSTRIES INC.
发明人： Morton, Steven Gregory
IPC分类号： G06F11/16 , G06F11/20
CPC分类号： G11C29/006
摘要： An array reconfiguration apparatus is employed in large integrated circuits and large systems. The apparatus makes use of spare wires and/or computation elements which are incorporated in the array. The apparatus uses spare wires in place of defective wires and/or the apparatus uses spare computation elements in place of defective computation elements so that an operational system may be created in spite of the occurrence of numerous manufacturing or lifetime faults. The excess wires are utilized as data input and output lines and as such each data line is associated with a bidirectional buffer/receiver (B/R). The bidirectional B/R's are capable of transmitting data in either direction as from an input terminal to an output terminal or vice versa. Each data line is connected to a bidirectional multiplexing device which has a control input. Control logic means has dynamically stored therein the assignment of each significant wire and each computation element. Only unreliable wires as between integrated circuits are switchable. The control logic selects operational elements as well as operational data lines and hence uses the spare data lines to make connections between the redundant elements on the circuit board so that an array configuration can be implemented in spite of multiple defects on the overall circuit board. The invention further discloses a simple method for computing the assignments of cells and wires to avoid the defects.
摘要翻译：在大型集成电路和大型系统中采用阵列重新配置装置。该装置利用并入阵列中的备用电线和/或计算元件。该设备使用备用电线来代替有缺陷的电线，和/或该设备使用备用计算元件来代替有缺陷的计算元件，从而即使出现许多制造或寿命故障，也可能创建操作系统。多余的线被用作数据输入和输出线，并且因此每个数据线与双向缓冲器/接收器（B / R）相关联。双向B / R能够从输入端子到输出端子沿任一方向传输数据，反之亦然。每个数据线连接到具有控制输入的双向多路复用装置。控制逻辑装置动态地存储每个有效线和每个计算元件的分配。集成电路之间只有不可靠的电线是可切换的。控制逻辑选择操作元件和操作数据线，因此使用备用数据线来在电路板上的冗余元件之间进行连接，使得即使在整个电路板上存在多个缺陷，也可以实现阵列配置。本发明还公开了一种用于计算单元和电线的分配以避免缺陷的简单方法。

49. 发明公开

EP0261164A1 RANDOM ADDRESS SYSTEM FOR CIRCUIT MODULES 失效
标题翻译：关于电路模块选择性寻址系统。
公开(公告)号：EP0261164A1
公开(公告)日：1988-03-30
申请号：EP87901599.0
申请日：1987-03-18
申请人： ANAMARTIC LIMITED
发明人： SINCLAIR, Alan, Welsh
IPC分类号： G06F11 , G06F12 , G06F15 , G11C29
CPC分类号： G11C29/006
摘要： Un circuit intégré à l'échelle d'une tranche comprend un réseau de puces ou de modules non-découpés (10), comprenant chacun un circuit de stockage ou de traitement de données, tel qu'une mémoire à accès sélectif dynamique, et un circuit logique à configuration. Des canaux (11) destinés à recevoir les données et les signaux de commande sont disposés entre chaque module et ses voisins N, S, E et W, un module cible situé dans le réseau pouvant être adressé par détermination d'un passage (12) allant d'un module d'entrée au module cible en passant par le réseau. L'adressage s'effectue en envoyant un courant d'ordres de liaison, donnant chacun à un module l'ordre de se lier sur l'un de ses voisins N, S, E et W. Chaque module répond au premier ordre du courant puis émet sur le courant dépouillé du premier ordre. Dans un autre mode de réalisation possible, les ordres de liaison sont transmis de module à module en parallèle et chaque module répond à l'ordre au niveau de l'extrémité la moins significative et l'élimine par une commutation des ordres dans la direction la moins significative avant le passage des ordres dans le prochain module. Un circuit de commande, servant à adresser des modules dans le réseau au hasard forment un seul groupe d'ordres de commande pour chaque module devant être adressé, ces groupes d'ordre étant conçus de telle sorte que les passages conduisant aux différents modules forment un arbre à branches denses commençant depuis le module d'entrée.

50. 发明公开

EP0240864A2 High-yield semiconductor memory devices 失效
标题翻译： Hochausbeute-Halbleiterspeichergeräte。
公开(公告)号：EP0240864A2
公开(公告)日：1987-10-14
申请号：EP87104534.0
申请日：1987-03-27
申请人： Hewlett-Packard Company
发明人： Keshner, Marvin S. , Eaton, Steven Glen
IPC分类号： G06F11/00
CPC分类号： G11C19/00 , G06F11/00 , G06F11/1008 , G06F11/26 , G11C8/12 , G11C29/006
摘要： Memory devices consist of small memory blocks memory (12) with very high yields (approximately97%). Each block (12) is capable of functioning whether or not neighboring blocks are defective. Blocks are interconnected with only five lines and communicate serially. External circuitry (42) contains ECC, a means for avoiding defective blocks and using spares, plus interface and control circuitry.
摘要翻译：存储器件由小的存储器块（12）组成，具有非常高的产量（约97％）。每个块（12）能够执行相邻块是否有缺陷。块只有五条线路互连，并且串行通信。外部电路（42）包含ECC，用于避免有缺陷的块和使用备件加上接口和控制电路的装置。

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